Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-03-22
2004-12-07
Thomas, Tom (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S294000, C438S303000, C438S585000, C438S639000
Reexamination Certificate
active
06828219
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device structure and to the process for forming the structure, and more particularly to a stacked spacer structure and process for its formation, which can effectively reduce coupling capacitance.
BACKGROUND OF THE INVENTION
The computer and the electronic industry consistently demand of increased overall speed as well as lower fabrication costs for integrated circuits. As far as a computer is concerned, doubtlessly, the integrated circuits, such as Dynamic Random Access Memory (DRAM), play a crucial role. A great number of DRAM memory cells are usually required, and thus they are a vital factor for determining the I/O speed of the computer. Hence, pursuing the miniaturization of the DRAM devices so as to lower costs as well as attain a high-speed performance is one major goal in the industry.
The miniaturization of devices according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant decreases in performance by degrading parasitic capacitance and resistance to be achieved, thus resulting in performance benefits. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. An example is self-aligned MOSFET devices, which are generally fabricated by forming a polysilicon gate electrode having self-aligned source/drain contact (SAC) areas adjacent to the gate electrode. These self-aligned MOSFET devices are preferred because of their small size, high packing density, low power consumption and low manufacturing cost.
Conventional self-aligned MOSFET devices are typically fabricated by patterning a stacked gate electrode layer comprised of a polysilicon layer and a silicon oxide cap layer over a gate oxide on the device areas of a single crystal semiconductor substrate. Insulating sidewall spacers, usually composed of silicon oxide, are formed next on the sidewalls of the stacked gate and insolate the conductive gate electrode layer from the adjacent SAC plugs.
Unfortunately, one problem occurs because much thinner oxide sidewall spacers are used to achieve the higher device density. A cleaning step is used to remove any native oxide left on the substrate, and the thin oxide sidewall spacers are attacked resulting in electrical shorts between the SAC plug and gate electrode.
Several methods for improving the self-aligned MOSFET devices are provided. A silicon nitride spacer is employed to replace the oxide sidewall spacer. Although the nitride sidewall spacer can be an etching stopper film that minimizes spacer consumption, a high dielectric constant of about 7 for the nitride sidewall spacer results in a serious coupling capacitance that also decreases the operation speed of devices as feature size enters the sub-half micron generation. Thus, this limits the degree to which the integrated density can be scaled down.
Therefore, there is still a strong need for thinner spacers with low coupling capacitance and improved electrical isolation in the semiconductor industry to provide more reliable self-aligned MOSFET devices or electrical inter-connections.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a stacked spacer structure to effectively isolate a conductive gate from a neighboring conductive layer by reducing gate sidewall spacer consumption during the etching process.
It is another object of the present invention to provide a stacked spacer structure to reduce coupling capacitance between two adjacent conductive layers by decreasing the effective dielectric constant.
In one aspect, the present invention provides a method of fabricating a stacked spacer structure. The method comprises the following steps. A semiconductor substrate having at least one stacked layer is provided. The stacked layer is composed of a conductive layer and a cap layer thereon. A dielectric layer substantially higher than the conductive layer is formed on the substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and the dielectric layer are sequentially etched to form a first spacer on the sidewalls of the stack layer. A second silicon nitride layer is formed over the substrate, and then is etched to form a second spacer on the sidewalls of the first spacer.
In another aspect, the present invention provides a method of fabricating a stacked spacer structure. The method comprises the following steps. A stacked layer having a conductive layer and a first dielectric layer thereon is formed on a semiconductor substrate. A second dielectric layer substantially higher than the conductive layer is formed on the substrate. A third dielectric layer is then formed over the substrate. The third dielectric layer and the second dielectric layer are sequentially etched to form a first spacer on the sidewalls of the stacked layer. A fourth dielectric layer is formed over the substrate and is etched to form a second spacer on the sidewalls of the first spacer. The second dielectric layer has a dielectric constant lower than that of the first, third and fourth dielectric layers.
In a further aspect, the present invention provides a stacked spacer structure on the sidewalls of a stacked layer formed on a semiconductor substrate. The stacked layer comprises a conductive layer and a cap layer thereon. A low dielectric bottom portion substantially higher than the conductive layer is formed on the substrate and on the sidewalls of the stacked layer. A silicon nitride top portion is formed on the low dielectric bottom portion and on the sidewalls of the stacked layer. The silicon nitride top portion and the low dielectric bottom portion construct an inner spacer. A silicon nitride outer portion is formed on the sidewalls of the low dielectric bottom portion and the silicon nitride top portion.
In a yet another aspect, the present invention provides a semiconductor structure adapted for a semiconductor substrate. At least one stacked layer comprising a conductive layer and a first dielectric layer is formed on the semiconductor substrate. A second dielectric layer substantially higher than the conductive layer is formed on the substrate and on the sidewalls of the stacked layer. A third dielectric layer is formed on the second dielectric layer and on the sidewalls of the stacked layer. The second and third dielectric layers construct an inner spacer. A fourth dielectric layer is formed on the sidewalls of the second and third dielectric layer. The second dielectric layer has a dielectric constant lower than that of the first, third and fourth dielectric layers.
The stacked spacer structure of the present invention can shrink the width of the stacked spacer and reduce coupling capacitance by embedding low dielectric constant material inside the spacer structure.
REFERENCES:
patent: 6281073 (2001-08-01), Lee
patent: 6326270 (2001-12-01), Lee et al.
patent: 6380042 (2002-04-01), Huang
patent: 6448140 (2002-09-01), Liaw
patent: 6562676 (2003-05-01), Ju
patent: 6573551 (2003-06-01), Kim et al.
patent: 6627504 (2003-09-01), Bertrand et al.
Chuang Yueh-Cheng
Sheu Bor-Ru
Yang Shih-Hsien
Dickinson Wright PLLC
Richards N. Drew
Thomas Tom
Winbond Electronics Corporation
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