Stacked sense-amp cache memory system and method

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365207, 365208, G11C 700

Patent

active

060943939

ABSTRACT:
A stacked sense-amp cache memory system and method is provided. The stacked sense-amp cache memory system (10) may comprise a memory cell array (22) coupled to a cache system (30). The memory cell array (22) stores and retrieves a data signal. Recently retrieved data signals are stored in the cache system (30). A column select system (32) is coupled to the cache system (30). A logic subsystem (12) controls the column select system (32) such that the column select system (32) directs the data signal from the memory cell array (22) to a sense-amp system (34) or directs a stored data output signal from the cache system (30) to a switching system (36). The sense-amp system (34) senses and amplifies the data signal and produces an amplified data output signal. The switching system (36) is coupled to the sense-amp system (34) and the cache system (30) and operates to select between the amplified data output signal from the sense-amp system (34) and the stored data output signal from the cache system (30).

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