Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2003-05-07
2004-11-16
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S787000, C257S777000, C257S723000
Reexamination Certificate
active
06818980
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to integrated circuit packaging, and more particularly to a stacked semiconductor die ball grid array package.
BACKGROUND OF THE INVENTION
High performance integrated circuit (IC) packages are well known in the art. Improvements in IC packages are driven by industry demands for increased thermal and electrical performance and decreased size and cost of manufacture.
Dynamic random access memory (DRAM) chips are commonly used in conjunction with flash memory chips in, for example, cellular phones, personal digital assistants (PDAs) and digital cameras. In particular, the DRAM chip is packaged in a single semiconductor package and mounted to a printed circuit board for use in a suitable application. Similarly, the flash memory chip is packaged in a single semiconductor package and is then mounted to the printed circuit board, adjacent the DRAM chip. The printed circuit board provides electrical connections for the two chips when assembled. Clearly, these two packages suffer from many disadvantages, including excessive space required for mounting two separate packages. Also, it is desirable to decrease printed circuit board assembly time and cost.
In one particular improvement to the above-described prior art, DRAM chips and flash memory chips have been encapsulated in a single package, in side-by-side relation to each other. Thus, a single, larger package is mounted to the printed circuit board on assembly. While this package provides the advantage of mounting only a single package containing both the DRAM and flash memory chips adjacent to each other, the package footprint is very large. It is desirable to reduce the package footprint and thereby reduce the area of the package on the printed circuit board.
It is therefore an object of an aspect of the present invention to provide an integrated circuit package and method of manufacturing the package that obviates or mitigates at least some of the disadvantages of the prior art.
SUMMARY OF THE INVENTION
In one aspect of the present invention, there is provided an integrated circuit package including a substrate having conductive traces therein. A first semiconductor die is mounted in a die-down configuration to a first surface of the substrate. A second semiconductor die is mounted to a backside of the first semiconductor die. A plurality of connectors electrically connect the first semiconductor die to portions of the conductive traces of the substrate and a plurality of wire bonds connect the second semiconductor die to other portions of the conductive traces of the substrate. An encapsulant encapsulates the wire bonds and covers at least a portion of the first surface of the substrate and the second semiconductor die. A ball grid array is disposed on a second surface of the substrate, bumps of the ball grid array being connected with the conductive traces.
In another aspect, there is provided a process for fabricating an integrated circuit package. The process includes: mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of the first semiconductor die; wire boding the second semiconductor die to portions of the conductive traces of the substrate; encapsulating the wire bonds between the second semiconductor die and the conductive traces of the substrate, in an encapsulant; wire bonding the first semiconductor die to other portions of the conductive traces of the substrate; encapsulating the wire bonds between the first semiconductor die and the substrate; and forming a ball grid array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of the conductive traces.
In one aspect, the first semiconductor die is a dynamic random access memory (DRAM) chip and the second semiconductor die is a flash memory chip. Advantageously, the second semiconductor die is stacked on the first semiconductor die, thereby providing a package including both semiconductor dice and having a smaller footprint than the conventional packages. Thus, the package requires less area when mounted on the motherboard, thereby aiding in reducing the size of the motherboard.
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patent: 2002/0089050 (2002-07-01), Michii et al.
patent: 2002/0090753 (2002-07-01), Pai et al.
patent: 2002/0105067 (2002-08-01), Oka et al.
patent: 2002/0144840 (2002-10-01), Tzu et al.
patent: 2003/0197284 (2003-10-01), Khiang et al.
ASAT Ltd.
Clark Jasmine
Keating & Bennett LLP
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