Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2003-03-03
2004-12-28
Zarneke, David (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S686000
Reexamination Certificate
active
06835598
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of priority of Korean Patent Application No. 2002-43696, filed 24 Jul. 2002 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor module including a stacked semiconductor package and a method of manufacturing the same.
2. Description of the Related Art
The demand for compact semiconductor devices with high memory capacities has resulted in the development of a stacked semiconductor package. In general, a stacked semiconductor package is manufactured by combining two semiconductor packages.
Such stacked semiconductor packages have been widely used in order to easily double the memory capacity of a semiconductor package. For instance, if a stacked semiconductor package is manufactured by combining two of the same semiconductor memory devices, the memory capacity of the semiconductor package is twice the capacity of each semiconductor memory device.
FIGS. 1 through 3
are cross-sectional views of conventional stacked semiconductor packages.
Referring to
FIG. 1
, a stacked semiconductor package
91
is a combination of two small out-line (SO) packages
10
and
20
, both of which are of a lead-on-chip (LOC) type, which are connected via a metal pattern
30
fixed on a chip adhesion layer
40
. The metal pattern
30
electrically connects corresponding leads of the two SO packages
10
and
20
.
Referring to
FIG. 2
, a stacked semiconductor package
92
is a combination of two LOC type SO packages
52
and
54
that are connected via solders
58
and a small-scale printed circuit board (PCB)
56
.
Referring to
FIG. 3
, a stacked semiconductor package
93
includes two chip scale packages (CSPs)
70
and
80
connected via a vertical-through hole
72
and solder balls
79
and
89
, which are external connection terminals. Here, the stacked semiconductor package
93
encapsulants
74
, a top polyimide layer
76
, gold wires
78
, semiconductor chips
82
, a bottom polyimide layer
84
, and a multi-layer type substrate
86
.
Conventional stacked semiconductor packages such as those described above and shown in
FIGS. 1
,
2
, and
3
, respectively, are connected to a module board only by external connection terminals, such as leads and solder balls. In such cases, a precondition exists that both semiconductor packages are physically and electrically connected to each other within the stacked semiconductor package in order to attach the stacked semiconductor package to the module board.
SUMMARY OF THE INVENTION
In exemplary embodiments, the present invention provides a stacked semiconductor module, which includes at least one stacked semiconductor package. In each stacked semiconductor package, two semiconductor packages are electrically connected to each other by means not within the stacked semiconductor package. In exemplary embodiments, the present invention also includes a method of manufacturing such a stacked semiconductor module.
In an exemplary embodiment, the stacked semiconductor module includes a module board to which one or more stacked semiconductor packages are mounted. Each stacked semiconductor package includes a lower chip scale package (CSP) and an upper CSP, which are electrically connected with each other by means of the module board.
In another exemplary embodiment, the lower CSP may be mounted to a respective mounting region of the module board, such that the lower CSP is electrically connected to the mounting region. A conductive interconnection tape may be used to electrically connect the upper CSP to tape adhesion regions of the module board, which are electrically connected to the mounting region.
According to another exemplary embodiment, the conductive interconnection tape may comprise either a copper pattern formed on a flexible base film. In another exemplary embodiment, the conductive interconnection tape may comprise an etched lead frame.
In another exemplary embodiment, the lower CSP includes external connection terminals that are electrically connected to the respective mounting region of the module board. A chip adhesion region is formed on the lower CSP to which an inverted upper CSP is attached, such that the external connection terminals of the upper CSP is exposed in an upward direction. The external connection terminals of the upper CSP are electrically connected to a mounting region of a conductive interconnection tape. The upper CSP mounting region of the conductive interconnection tape is electrically connected to bonding regions at the ends of the conductive interconnection tape. These bonding regions are bonded and to tape adhesion regions on the module board, such that each bonding region is electrically connected to the respective tape adhesion region. The module board's tape adhesion regions are in turn electrically connected to the lower CSP mounting regions of the module board.
The lower CSP mounting region of the module board and the upper CSP mounting region of the conductive interconnection tape are configured to receive the particular type of external connection terminals utilized the lower CSP and upper CSP, respectively. For example, the upper and lower CSPs may each include either solder balls or solder bumps as their external connection terminals.
In another exemplary embodiment of the present invention, a large heat spread plate may be formed over an exposed side of a conductive interconnection tape. The heat spread plate may be attached to the conductive interconnection tape by means of a thermal interface material (TIM).
According to another exemplary embodiment, the stacked semiconductor module may include an outwardly exposed large-scale heat sink. The heat sink may be formed such that it connects a plurality of conductive interconnection tapes and stacked semiconductor packages of the stacked semiconductor module.
By providing for a CSP to be stacked upon another CSP to build a stacked semiconductor package on a module board, exemplary embodiments of the present invention facilitates the manufacture of stacked semiconductor modules. Furthermore, heat generated within such a stacked semiconductor module may be effectively discharged using a heat spread plate and/or a large-scale heat sink according to exemplary embodiments of the present invention.
REFERENCES:
patent: 5675180 (1997-10-01), Pedersen et al.
patent: 5837566 (1998-11-01), Pedersen et al.
patent: 5843807 (1998-12-01), Burns
patent: 5891761 (1999-04-01), Vindasius et al.
patent: 6168973 (2001-01-01), Hubbard
patent: 6177296 (2001-01-01), Vindasius et al.
patent: WO 03037053 (2003-05-01), None
Baek Joong-hyun
Im Yun-hyeok
Lee Jin-yang
Lee Tae-koo
Harness & Dickey & Pierce P.L.C.
Harrison Monica D.
Samsung Electronics Co,. Ltd.
Zarneke David
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