Stacked semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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Details

C365S051000, C365S063000

Reexamination Certificate

active

11151220

ABSTRACT:
The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

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patent: 6487102 (2002-11-01), Halbert et al.
patent: 6594169 (2003-07-01), Sakui
patent: 7099173 (2006-08-01), Koide
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patent: 2001-035152 (2001-02-01), None
patent: 2002-026283 (2002-01-01), None
patent: 2003-204030 (2002-07-01), None
patent: 2003-209222 (2003-07-01), None
patent: 2004-102781 (2004-04-01), None

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