Static information storage and retrieval – Read only systems – Semiconductive
Patent
1997-04-02
1999-09-07
Dinh, Son T.
Static information storage and retrieval
Read only systems
Semiconductive
365182, 257390, G11C 1700
Patent
active
059497041
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuit memory; and more particularly high density read-only memory ROM devices.
2. Description of Related Art
ROM devices include an array of ROM cell transistors which permanently store data, such as computer programs, in electronic devices. ROM devices are preferred over other types memory because they provide high density, low cost storage for data which does not need to be changed during the operation of the system incorporating the ROM. One high density read-only memory architecture is described in U.S. Pat. No. 5,117,389 entitled FLAT CELL READ-ONLY INTEGRATED CIRCUIT invented by Yiu, issued May 26, 1992. Other example architectures are described in Millman, MICROELECTRONICS, McGraw-Hill (New York, 1979), Section 9-3, pages 276-283.
The density of ROM cells on an integrated circuit is directly related to the cost of storing data. Thus, the manufacturing techniques for ROM devices have developed to provide higher and higher density architectures. One primary approach to achieving higher density is improvements in manufacturing processes which allow for smaller line widths.
An alternative technique for increasing the density of ROM devices has been proposed in U.S. Pat. No. 5,383,149 entitled "ULSI Mask ROM Structure and Method of Manufacture," invented by Hong, issued Jan. 17, 1995. In the Hong patent, a double-density device is provided by stacking two arrays of ROM cells, with one array above and with one array below a shared wordline array. The bottom array of ROM cells is formed using n-channel transistors, while the top array of ROM cells is formed using p-channel transistors in the Hong design. This use of different conductivity types in the transistors has a number of deficiencies. First, the wordlines must drive different polarities of wordline signals depending on whether the p-channel or n-channel transistor arrays are being sensed. Second, an asymmetry in the design occurs because p-channel transistors are slower than n-channel transistors. Therefore, the n-channel transistor array has a faster access time than the p-channel transistor array, slowing the overall speed of the device. Furthermore, the mask ROM code implant steps used in the two types of array require different materials and processing steps. This increases the complexity, the number of steps and the cost of the manufacturing process.
Accordingly, it is an object of the present invention to provide a high density ROM device, overcoming the disadvantages of the Hong approach, and providing even greater density.
SUMMARY OF THE INVENTION
The present invention provides a stacked ROM device which utilizes the same conductivity type for the ROM cells in both the top and the bottom ROM cell matrixes. This provides substantial advantages by reducing the complexity of the manufacturing process, allowing for dense array architectures, and simplifying the implant steps for coding the stacked ROM cell matrixes.
Accordingly, the present invention can be characterized as a ROM device which comprises a first ROM cell matrix including conductively doped source and drain lines having a first conductivity type in a semiconductor substrate having a second conductivity type. For example, the source and drain lines are implemented with n-type doping in a p-type substrate. A second ROM cell matrix comprises conductively doped source and drain lines having the first conductivity type in a semiconductor layer which overlies and is isolated from the semiconductor substrate. A plurality of shared wordlines is disposed between the first and second ROM cell matrixes. A plurality of bit lines is isolated from and overlies the semiconductor layer. A plurality of matrix select transistors is coupled between the conductively doped source and drain lines in the first ROM cell matrix, and the plurality of bit lines, and between the conductively doped source and drain lines in the second ROM cell matrix and the plurality of bit lines, to selective
REFERENCES:
patent: 5017978 (1991-05-01), Middelhoek et al.
patent: 5117389 (1992-05-01), Yiu
patent: 5383149 (1995-01-01), Hong
patent: 5644532 (1997-07-01), Chang
Dang-hsing Yiu Tom
Shone Fu-Chia
Dinh Son T.
Macronix International Co. Ltd.
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