Stacked package structure

Details Stacked package structure Stacked package structure

2007-07-10

2007-07-10

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE25013

Reexamination Certificate

active

11409933

ABSTRACT:
A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.

REFERENCES:
patent: 5883426 (1999-03-01), Tokuno et al.
patent: 6101100 (2000-08-01), Londa
patent: 6740964 (2004-05-01), Sasaki
patent: 7049692 (2006-05-01), Nishimura et al.
patent: 2004/0080036 (2004-04-01), Chang et al.
patent: 2006/0180911 (2006-08-01), Jeong et al.

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