Stacked package and method of manufacturing the same

Details Stacked package and method of manufacturing the same Stacked package and method of manufacturing the same

2008-05-05

2011-10-04

Clark, Sheila (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

08030747

ABSTRACT:
In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.

REFERENCES:
patent: 6031281 (2000-02-01), Kang et al.
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6476467 (2002-11-01), Nakamura et al.
patent: 7239164 (2007-07-01), Tamaki
patent: 7569922 (2009-08-01), Ogata
patent: 2008/0197509 (2008-08-01), Yamaguchi et al.
patent: 2009/0045497 (2009-02-01), Kagaya et al.
patent: 1020020015215 (2002-02-01), None
patent: 10-0583491 (2006-05-01), None
English Language Abstract of KR 1020010094894 dated Nov. 3, 2001.

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