Stacked offset semiconductor package and method for fabricating

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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C257SE23172, C257SE25013, C257SE23176, C257SE25011, C257SE21536, C257SE23052, C257SE25029, C257SE23146, C257SE23145, C257SE23079, C257SE23125, C257SE23142, C257S777000, C257S723000, C257S784000, C257S786000, C257S698000, C257S685000, C257SE23036

Reexamination Certificate

active

10763164

ABSTRACT:
In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

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