Stacked memory module and system

Details Stacked memory module and system Stacked memory module and system

2009-05-12

2011-10-04

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

Reexamination Certificate

active

08031505

ABSTRACT:
A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

REFERENCES:
patent: 6133640 (2000-10-01), Leedy
patent: 6768163 (2004-07-01), Tanaka et al.
patent: 7078793 (2006-07-01), Ruckerbauer et al.
patent: 7123497 (2006-10-01), Matsui et al.
patent: 7320100 (2008-01-01), Dixon et al.
patent: 2008/0204091 (2008-08-01), Choo et al.

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