Stacked memory device

Details Stacked memory device Stacked memory device

2011-08-16

2011-08-16

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23012, C257S678000, C257S777000, C257S723000, C257SE23013

Reexamination Certificate

active

07999367

ABSTRACT:
A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

REFERENCES:
patent: 6740981 (2004-05-01), Hosomi
patent: 2006/0076676 (2006-04-01), Fratti
patent: 2007/0228546 (2007-10-01), So et al.
patent: 2003060153 (2003-02-01), None
patent: 1020060074146 (2006-07-01), None

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