Stacked memory and fuse chip

Details Stacked memory and fuse chip Stacked memory and fuse chip

2009-02-25

2011-10-18

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S063000

Reexamination Certificate

active

08040745

ABSTRACT:
A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.

REFERENCES:
patent: 7053470 (2006-05-01), Sellers et al.
patent: 7222274 (2007-05-01), Combs et al.
patent: 2007/0075396 (2007-04-01), Ogishima
patent: 2004-119458 (2004-04-01), None

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