Stacked integrated circuit structure

Details Stacked integrated circuit structure Stacked integrated circuit structure

2000-10-10

2002-04-30

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S685000, C257S686000

Reexamination Certificate

active

06380624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked integrated circuit stacked structure. More particularly, the present invention relates to a stacked integrated circuit structure in which a substrate is employed as a stacking medium between the leads of the stacked integrated circuits.
2. Description of the Prior Art
In this information-centered world, integrated circuits are closely related to daily living. Commodities composed of integrated circuits are currently in use in all aspects of living. As electronic technique improves, electronic products having more powerful functions and that are more humanized are being manufactured. They all have the same design goal of being lightweight and small in size in order to provide comfortable usage. The mass production of 0.18 microns integrated circuits is currently achieved, and many other micro-packaging structures, for example, the chip scale package (CSP), the wafer level package, the multichip module (MCM), etc. have been developed successfully. In addition, the assembly technique for electronic elements also includes the high-density multi-level PCB, which allows IC packages to be arranged closer together on the PCB.
Therefore, stacked packaging structures are currently in development. By means of the packaging structure design, packaged ICs can be stacked on top of each other in a three-dimensional structure. A prior art stacked packaging structure is schematically shown in FIG.
1
. Semiconductor dice
100
a
,
100
b
are connected to leadframes
104
a
,
104
b
by means of bonding wires
102
, and enveloped by a molding compound
106
, for example, epoxy, to form individual packages
108
a
,
108
b
, respectively. Differences in bending of outer leads of the leadframes
104
a
,
104
b
are employed to establish a three-dimensional stacked structure for the packages
108
a
,
108
b
as shown in FIG.
1
.
Because direct connections between the leads are used in the stacked structure of prior art, the assembly process is not easy to control, Electrical shorts between the leads may occur due to deformations of the leads caused by external forces, especially for those products having high leads positions and small leads separations. Moreover, additional apparatus are required for the assembly of the prior art stacked structure for mass production.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a stacked integrated circuit structure, which employs a substrate as a stacking medium between leads of stacked integrated circuits, whereby increasing the tightness of leads connections.
The second object of the present invention is to provide a stacked integrated circuit structure which does not require additional apparatus for mass production.
The third object of the present invention is to provide a stacked integrated circuit structure which is applicable to the memory module. Thus, the memory size can be increased but not the overall area. Hence, the assembly density is increased.
The fourth object of the present invention is to provide a stacked integrated circuit structure which makes the production and the assembly of the memory module easier.
The fifth object of the present invention is to provide a stacked integrated circuit structure, in which circuitry and electronic elements of the memory module can be directly mounted on the substrate used for stacking. Thus, the goal of manufacturing process integration can be accomplished.
To achieve these objects and other advantages and in accordance with the purpose of the present invention, a stacked integrated circuit structure is described herein. A plurality of main package bodies of a plurality of integrated circuits are stacked on each other, with a stacking substrate aligned between leads of the stacked integrated circuits for connection means. Therein, each of two surfaces of the stacking substrate includes a plurality of terminals electrically connected to the corresponding leads. The stacking substrate also contains a plurality of through vias connecting the corresponding terminals on the two surfaces. For two integrated circuits stacked on each other, a hole can be defined in the stacking substrate to house a main package body of one of the integrated circuits, or by means of individually separated substrates arranged around a perimeter of a main package body of one of the integrated circuits, so that the thickness of the stacked integrated circuits is reduced.
While employing the stacked integrated circuit structure of the present invention to a memory module, a plurality of holes is defined on a substrate. A plurality of terminals is located on two surfaces of the substrate as well. A main package body of an integrated circuit is housed in each of the holes, with leads of the integrated circuit electrically connected to the terminals on a first surface of the substrate. An integrated circuit is stacked on a second surface corresponding to each of the hole positions, with leads connected to the corresponding terminals. In addition, a plurality of recesses is located on the first surface. A module circuit board includes traces, electronic elements, and golden fingers, which are electrically connected to each other. During the assembly process, the first surface of the stacking substrate faces the module circuit board for connections, with the electronic elements received in the recesses, and the terminals on the first surface electrically connected to the traces.
Another application to a memory module is the direct fabrication of traces on a substrate, with electronic elements directly inserted into the substrate and electrically connected to the traces. Connecting the whole stacked structure to a circuit board with golden fingers then forms a memory module.


REFERENCES:
patent: 6013948 (2000-01-01), Akram et al.
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6291892 (2001-09-01), Yamaguchi

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