Stacked gate nonvolatile semiconductor memory and method for...

Details Stacked gate nonvolatile semiconductor memory and method for... Stacked gate nonvolatile semiconductor memory and method for...

2007-10-30

2011-11-08

Menz, Douglas (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000

Reexamination Certificate

active

08053825

ABSTRACT:
A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.

REFERENCES:
patent: 6396101 (2002-05-01), Patelmo et al.
patent: 6720579 (2004-04-01), Shin et al.
patent: 7582927 (2009-09-01), Isobe et al.
patent: 2006/0244018 (2006-11-01), Kutsukake et al.
patent: 2006-310454 (2006-11-01), None

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