Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-02-28
2002-11-05
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S306000
Reexamination Certificate
active
06476460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to making of power semiconductor input/output circuits and more particularly for multiple voltage applications and devices manufactured thereby.
2. Description of Related Art
U.S. Pat. No. 3,897,282 of White for a “Method of Forming Silicon Gate Device Structures with Two or More Gate Levels” describes the method for forming a gate device with two or more gate levels at Col. 1, lines 29-40, col. 2, line 63 to col. 3, line 2;
FIGS. 4-7
and FIG.
9
. White shows the general principle of forming a FET gate with multiple polysilicon layers separated by dielectric layers, but does not teach providing various power supply levels.
U.S. Pat. No. 5,324,676 of Guterman describes a “Method for Forming a Dual Thickness Dielectric Floating Gate Memory Cell.”
U.S. Pat. No. 5,604,367 of Yang for “Compact EEPROM Memory Cell Having a Floating Gate Transistor with a Multilayer Gate Electrode” shows a method for forming a memory cell having a floating gate transistor with a multi-layer gate electrode.
U.S. Pat No. 5,606,521 of Kuo for “Electrically Erasable and Programmable Read Only Memory with Non-Uniform Dielectric Thickness” shows forming a memory cell with non-uniform dielectric thicknesses.
U.S. Pat. No. 5,644,528 of Kojima for “Non-Volatile Memory Having a Cell Applying to Multi-Bit Data Layered Floating Gate Architecture and Programming Method for the Same” shows a method of forming a multi-bit memory cell having multiple layered floating gate.
In the past the goal of providing multiple voltage power supplies has been achieved by the steps as follows:
1. Provide multiple gate dielectrics with different thicknesses to handle various external internal power supplies.
2. Regrow silicon oxides by performing a complicated process resulting in serious reliability: issues.
SUMMARY OF THE INVENTION
An object of this invention is to eliminate the dual or triple gate dielectric process.
Another object of this invention is to relax product design constraints, and to provide better process reliability.
In accordance with this invention, a method is provided for manufacture of a device on a semiconductor substrate with a capacitor formed to provide split voltages for semiconductor circuits described by the following steps. Form an active area in the substrate serving as the lower capacitor plate of a bottom capacitor. Form a thin dielectric layer and field oxide regions over the substrate. Form a first upper capacitor plate, preferably composed of a first doped polysilicon layer, over the thin dielectric layer above the active area completing the bottom capacitor. Form a thick dielectric layer over the first upper capacitor plate. Form a via through the thick dielectric layer connecting to the first upper capacitor plate. Form a third capacitor plate, preferably composed of a second doped polysilicon layer, over the dielectric layer above the active area to complete the bottom capacitor. The third plate can also serve as a lower plate for a top capacitor. Form an inter-layer dielectric layer over the second plate. Form an upper capacitor layer, preferably composed of a third doped polysilicon layer, over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor.
Preferably, the bottom capacitor has a first effective plate area and the top capacitor has a different effective plate area which provides the different capacitance value, and the voltage Veq across the upper and bottom capacitor connected in series between a source and reference potential is expressed by the equation as follows:
Veq=Vg
1
+
Vg
2
=(
Vcc−Vss
);
and
the voltage Vg
2
across the thin dielectric layer is expressed by the equation as follows:
Vg2
=
(
Vcc
-
Vss
)
*
C
1
(
C
1
+
C
2
)
.
Preferably, the inter-layer dielectric layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride and combinations thereof.
In accordance with another aspect of this invention, a device formed on a semiconductor substrate includes a capacitor which provides split voltages for semiconductor circuits. The device includes an active area in the substrate serving as a lower capacitor conductive plate for a bottom capacitor. Field oxide regions and a thin dielectric layer are formed over the substrate. A first upper capacitor conductive plate is formed over the dielectric layer above the active area to complete the bottom capacitor. The first upper capacitor conductive plate is connected through a via connecting that plate to serve as a part of the lower capacitor conductive plate for the top capacitor also. An inter-layer dielectric layer is formed over the first upper capacitor conductive plate. A second upper capacitor layer is formed over the inter-layer dielectric layer to complete the top capacitor with a different capacitance value from the bottom capacitor.
Preferably, the bottom capacitor has a first effective plate area and the top capacitor has a different effective plate area which provides the different capacitance value.
Preferably, the voltage Veq across the upper and bottom capacitor connected in series between a source and reference potential is expressed by the equation as follows:
Veq=Vg
1
+
Vg
2
=(
Vcc−Vss
);
and
the voltage Vg
2
across the thin dielectric layer is expressed by the equation as follows:
Vg2
=
(
Vcc
-
Vss
)
*
C
1
(
C
1
+
C
2
)
.
Preferably, the bottom capacitor has a first effective plate area and the top capacitor has a different effective plate area which provides the different capacitance value.
The voltage Veq across the upper and bottom capacitor connected in series between a source and reference potential is expressed by the equation as follows:
Veq=Vg
1
+
Vg
2
=(
Vcc−Vss
);
and
the voltage Vg
2
across the thin dielectric layer is expressed by the equation as follows:
Vg2
=
(
Vcc
-
Vss
)
*
C
1
(
C
1
+
C
2
)
.
Preferably, the inter-layer dielectric layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride and combinations thereof.
REFERENCES:
patent: 3897282 (1975-07-01), White
patent: 4685197 (1987-08-01), Tigelaar et al.
patent: 4700457 (1987-10-01), Matsukawa
patent: 4914546 (1990-04-01), Alter
patent: 5266507 (1993-11-01), Wu
patent: 5324676 (1994-06-01), Guterman
patent: 5463235 (1995-10-01), Ishii
patent: 5604367 (1997-02-01), Yang
patent: 5606521 (1997-02-01), Kuo et al.
patent: 5644528 (1997-07-01), Kojima
patent: 6137153 (2000-10-01), Le et al.
Lee Jin-Yuan
Liang Mong-Song
Yoo Choe-San
Ackerman Stephen B.
Jones II Graham S.
Loke Steven
Owens Douglas W.
Saile George O.
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