Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-07-10
2007-07-10
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257SE21676, C257SE27054
Reexamination Certificate
active
10714243
ABSTRACT:
A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
REFERENCES:
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5616510 (1997-04-01), Wong
patent: 5739567 (1998-04-01), Wong
patent: 5768192 (1998-06-01), Eitan
patent: 6002152 (1999-12-01), Guterman et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6040210 (2000-03-01), Burns et al.
patent: 6093945 (2000-07-01), Yang
patent: 6103573 (2000-08-01), Harari et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6281545 (2001-08-01), Liang et al.
patent: 6316315 (2001-11-01), Hofmann et al.
patent: 6329685 (2001-12-01), Lee
patent: 6420231 (2002-07-01), Harari et al.
patent: 6426896 (2002-07-01), Chen
patent: 6444525 (2002-09-01), Lee
patent: 6541815 (2003-04-01), Mandelman et al.
patent: 6597036 (2003-07-01), Lee et al.
patent: 6952034 (2005-10-01), Hu et al.
patent: 2002/0056870 (2002-05-01), Lee et al.
patent: 2002/0163031 (2002-11-01), Lee et al.
patent: 2004/0087084 (2004-05-01), Hsieh
Hayashi et al., “A Self-Aligned Split-Gate Flash EEPROM Cell With 3-D Pillar Structure,” pp. 87-88, 1999 Symposium on VLSI Technology Digest Of Technical Papers, Center for Integrated Systems, Stanford University, Stanford, CA 94305, USA.
IEEE, 2002, entitled “Quantum-well Memory Device (QW/MD) With Extremely Good Charge Retention,” Z. Krivokapic, et al. (4 pages).
Chen Bomy
Frayer Jack Edward
Lee Dana
Tran Hieu Van
DLA Piper (US) LLP
Huynh Andy
Nguyen Dao H.
Silicon Storage Technology, Inc.
LandOfFree
Stacked gate memory cell with erase to gate, array, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked gate memory cell with erase to gate, array, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked gate memory cell with erase to gate, array, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3819410