Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-06-24
1999-06-15
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257404, 257336, H01L 29788
Patent
active
059124881
ABSTRACT:
Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate. During programming, this EEPROM unit cell provides efficient mid-channel injection at high rates and at relatively low voltage levels and avoids many of the limitations associated with conventional stacked-gate EEPROM devices which typically provide less efficient drain-side injection and require relatively high voltage levels during programming. In particular, mid-channel injection of hot electrons from the channel region to the floating gate (within the stacked-gate electrode) is promoted by tailoring the conductivity of the channel region so that pinch-off occurs at a midpoint in the channel region during programming operations.
REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4794565 (1988-12-01), Wu et al.
patent: 5032881 (1991-07-01), Sardo et al.
patent: 5041886 (1991-08-01), Lee
patent: 5235544 (1993-08-01), Caywood
patent: 5422844 (1995-06-01), Wolstenholme et al.
patent: 5488245 (1996-01-01), Shimizu et al.
patent: 5554553 (1996-09-01), Harai
patent: 5646430 (1997-07-01), Kaya et al.
patent: 5719422 (1998-02-01), Burr et al.
A. T. Wu et al., A Source-Side Injection Erasable Programmable Read-Only-Memory (SI-EPROM) Device, IEEE Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986, pp. 540-542.
Cho Myoung-kwan
Kim Dae Mann
Hardy David B.
Postech Foundation
Samsung Electronics Co,. Ltd
LandOfFree
Stacked-gate flash EEPROM memory devices having mid-channel inje does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked-gate flash EEPROM memory devices having mid-channel inje, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked-gate flash EEPROM memory devices having mid-channel inje will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-404266