Stacked flip-chip integrated circuit assemblage

Details Stacked flip-chip integrated circuit assemblage Stacked flip-chip integrated circuit assemblage

1999-08-31

2002-01-15

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S737000, C257S778000

Reexamination Certificate

active

06339254

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit devices, and in particular to an arrangement for integrated circuit assembly.
BACKGROUND OF THE INVENTION
Maximizing performance, lowering cost and increasing the density of integrated circuits are ongoing goals of the electronics industry. In particular, portable systems, such as computers and telecommunications have spurred the efforts to define reliable technology for supplying circuits in the smallest possible area, and for many applications with increased operating speed.
Advances in interconnect technology have provided the key enablers toward these ends. Direct connection of the active surface of a semiconductor die to a substrate or package, using solder balls for flip-chip attachment, furnished the basic technology for low inductance, area array assembly of integrated circuits. This technology developed years ago has surged recently as more practical means of forming and attaching bump terminals has evolved. New methods including plating solders, or using solder or conductive polymers to adhere conductive spheres or columns to pads on the device have begun to replace the original process of evaporating and patterning solders.
Not only are chips attached to substrates by flip-chip connections replacing wire bonding, but ball grid array (BGA) and chip scale packages (CSP) are attached to boards or other next level interconnection by means of balls or bumps, rather than by leads. Ball sizes vary from those in the range of 75 microns used for flip-chip attachment to those greater than a millimeter in diameter for CSP and BGA attachment.
FIG. 1
provides a cross sectional view of a prior flip-chip
105
assembly in a BGA package
106
, and demonstrates the use of different ball sizes, i.e. solder balls
115
on the flip-chip assembly typically yield a stand off height of about 65 microns, whereas balls
116
on the BGA package have about 0.9 mm stand off. Not only is performance enhanced by lower inductance of short, wide ball connections, versus long, thin wire bond or lead conductors, but arraying the terminals in the area under the device, rather than at the perimeter minimizes space, and thereby supports increased packing density.
While bump or ball interconnect technology allows a mechanism for low inductance assembly of semiconductor devices, multichip modules provide a means for fabricating subsystems by interconnecting chips on a common substrate or package.
FIG. 2
demonstrates an example of such an assemblage wherein a die
201
may be connected by flip-chip terminals
202
or by wire bonds
203
to the substrate. The substrate
211
provides the wiring connection both between the chips within the assembly, and to external contacts
230
which in turn contact the next level of interconnection, such as a printed wiring board
220
. In multichip assemblies interconnections between chips often provides a means for decreasing the total number of output pins on the module, as compared to the number required for individual components, and thereby decreases the printed circuit board space required. Performance is enhanced as a result of shorter interconnections with lower inductance. In addition, common power and ground lines further decrease the input/outputs requirements and provide enhanced performance; multichip modules having multilevel substrates frequently include such designs.
Another technique for increasing density of integrated circuit devices has been stacked packages and/or stacked chips. Double-sided printed wiring boards with surface mount packages on each side was a forerunner of stacking packages face-to-face. There have been many iterations of stacked assemblies, including memory modules either as chips or packaged devices wherein the devices of similar device size and type are stacked back-to-front with vertical electrical interconnections on the perimeter.
Alternately, chips have been stacked face-to-face on a common wiring board. One such assembly, shown in
FIG. 3
provides a first flip-chip
301
positioned face-to-face with a second flip-chip
302
on a substrate
303
interposed between the chips to provide electrical connection
313
among the flip-chip terminals
311
, and to external circuitry
315
. However, this assembly uses a flex circuit as the interposer
303
between the facing flip-chips and requires a separate mechanical support
320
, which in turn has contact connections to the next level of interconnection. This results in a complex assembly.
It would be advantageous to develop a technique for increasing the packing density of integrated circuits which takes advantage of the low inductance of ball connections, the decreased number of input/output contacts as found with multichip or stacked assembly, good thermal dissipation, and the low cost of standardized packaging technology.
SUMMARY OF THE INVENTION
It is the primary object of the present invention to provide a novel packaging structure for improvement of packing density and performance of integrated circuits. The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
It is an object of this invention to provide a high density multichip assemblage wherein the active circuits are within the area of the largest single integrated circuit device in said assemblage.
The device of this invention includes two or more integrated circuit dice having flip-chip terminals, and a rigid substrate having a surface with printed wiring interconnections and a plurality of flip-chip pads. The device provides that a die having perimeter bump terminals is located on top of a smaller die or dice having bump terminals, bumps from all dice are aligned to pads on the substrate, and are electrically connected.
It is further an object of this invention to provide a stacked multichip assemblage having multiple packaging options, including BGA, CSP, cavity down BGA, cavity down CSP, Board-on-Chip(BOC), or chips directly attached to a printed wiring board. The assemblages may be encapsulated by a protective material such as an epoxy or ceramic layer, which in turn may have heat spreaders attached for improved thermal performance, but it should be noted that the encapsulation layer is not required to effectuate the purpose of the present invention.
It is also an object of this invention to provide a stacked flip-chip device wherein the effects of thermally induced mechanical stress on the bump terminals is minimized by having larger bumps on those die with maximum thermal mismatch to the substrate, and further reducing the effects of stress by encasing the bump connections of all die with an underfill material.
Another object of the invention is to provide a stacked multichip assemblage having good thermal dissipation as a result of multiple thermal conduction paths.
It is an object of this invention to provide a stacked chip assembly having low inductance advantages realized from bump connections, and from short interconnections between chips.
It is still further an object of this invention to provide a stacked flip-chip assembly which is capable of having fewer external input/output connections than would be required for each of the individual chips.
It is yet another objective of this invention that the bump terminals comprise electrically and thermally conductive materials, wherein provisions can be made for an assembly thermal hierarchy.
It is still further an objective of this invention to provide a stacked flip-chip assembly wherein the largest chip has perimeter contacts, and the smaller chips have latitude for perimeter, center or area arrayed terminals.
In accordance with the present invention, there is provided a method for forming the mechanical and electrical connection of the multiple chips of the stacked flip-chip assembly to the substrate in a single reflow process. The technique is applicable to packaging options such as BGA, CSP and/or directly attached to a printed circuit board.
The drawings constitute a part of this specificat

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