Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Patent
1996-05-24
1998-09-08
Lorin, Francis J.
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
29831, 29850, 156300, H05K 332
Patent
active
058040048
ABSTRACT:
A method for fabricating a multichip module includes attaching a first integrated circuit to a silicon circuit board. Bonding pads on the first integrated circuit are wire-bonded to a first set of contacts on the circuit board. A second integrated circuit is adhesively attached onto the top of the first integrated circuit. The second integrated circuit includes a recessed bottom surface to provide an overhang over the first integrated circuit which exposes the bonding pads on the top surface of the first integrated circuit. Then bonding pads on the second integrated circuit are wire-bonded to a second set of contacts on the circuit board.
REFERENCES:
patent: 3748479 (1973-07-01), Lehovec
patent: 4320438 (1982-03-01), Ibrahim et al.
patent: 4567643 (1986-02-01), Droguet et al.
patent: 4761681 (1988-08-01), Reid
patent: 4953005 (1990-08-01), Carlson et al.
patent: 4983533 (1991-01-01), Go
patent: 4996583 (1991-02-01), Hatada
patent: 5019943 (1991-05-01), Fassbender et al.
patent: 5019946 (1991-05-01), Eichelberger et al.
patent: 5146312 (1992-09-01), Lim
patent: 5214844 (1993-06-01), McWilliams et al.
patent: 5239447 (1993-08-01), Cotues et al.
patent: 5291061 (1994-03-01), Ball
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5434745 (1995-07-01), Shokrgozar et al.
A. Barfknecht et al., "Multichip Packaging Technology With Laser-Patterned Interconnects", IEEE Trans. Components, Hybrids, and Manufacturing Technology, vol. 12, No. 4, (1989)., pp. 646-649.
A.G. Bernhardt et al., "Multichip Packaging for Very-High-Speed Digital Systems", Applied Surface Science, vol. 46, pp. 121-130, (1990).
J. Drumm, "Bump and Lead Plating for High Density Interconnect Technology Development", Texas Instruments, Dallas, TX, pp. 670-682.
Hagge, "Ultra-Reliable Packaging for Silicon-on-Silicon WSI", IEEE Transactions on Components, Hybrids and Manufacturing, vol. 12, No. 2, pp. 170-179, (Jun. 1989).
K. Hatada et al., "Vertically Interconnected T-BTAB Devices for High Density Modules", Proc. of IEPS, pp. 645-650.
Maliniak, "Low-Cost Multichip Modules Push Limits of Packaging", Electronic Design International, (Jul. 1990).
J. Salzer, "Evaluating the Economic Factors of Automated Chip Bonding", Microelectronic Methods, pp. 29-31, (Feb. 1975).
S. Shanken et al., "Very High Density 3-D Packaging of Integrated Circuits", ISHM 89 Proceedings, Baltimore, MD, pp. 131-137, (1989).
Spielberger et al., "Silicon-on-Silicon Packaging", IEEE Transactions on Components Hybrids and Manufacturing Technology, vol. CHMT-7, No. 2, pp. 193-196, (Jun. 1984).
S. Stephansen et al., "Low Cost High Performance Silicon-on-Silicon Multichip Modules", Proc. Wescon, pp. 728-732, (Nov. 1990).
M. Suer, "A Prospective on 3-D IC Packaging", pp. 36.
D. Tuckerman, "Ultrahigh Thermal Conductance Microstructures for Cooling Integrated Circuits", 32nd Electronic Components Conf., pp. 145-149, (May 1982).
C. Val, "The 3D Interconnection Applications for Mass Memories and Microprocessors", Thomson CSF/DOI, France, pp. 851-860.
Val et al., "3-D Interconnection for Ultra-Dense Multichip Modules", IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 13, No. 4, pp. 814-821, (Dec. 1990).
A. Weinberg, "High Density Electronic Packaging Utilizing Vertical Integration and Low Temperature Cofired Ceramics", ISHM '90 Proceedings, pp. 618-625, (1990).
Whitworth, "A Complex Tab for Space Hybrids", ISHM 1989 Proceedings, Baltimore, MD., pp. 612-619, (1989).
Wolfe, "Electronic Packaging Issue in the 1990s", Electronic Packaging and Production, (Oct. 1990).
"Insulation Coated Bonding Wire", Tanaka Information, (1990).
Brathwaite Nicholas E.
Flatow Kirk
Marella Paul
Tuckerman David B.
Lorin Francis J.
nCHIP, Inc.
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