Stacked device manufacturing method

Details Stacked device manufacturing method Stacked device manufacturing method

2009-10-08

2010-12-28

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S109000, C438S460000, C438S461000, C438S463000, C438S464000, C257SE21499, C257SE21599

Reexamination Certificate

active

07858497

ABSTRACT:
A stacked device manufacturing method including a kerf forming step of forming a kerf on the front side of each of plural wafers along each street, the kerf having a depth corresponding to a predetermined finished thickness of each wafer, a first stacking step of stacking a first one of the wafers and a second one of the wafers in such a manner that the front side of the second wafer is opposed to the front side of the first wafer and that the electrodes of the second wafer are respectively bonded to the electrodes of the first wafer, a first back grinding step of grinding the back side of the second wafer to expose each kerf of the second wafer to the back side of the second wafer, a second stacking step of stacking a third one of the wafers to the second wafer in such a manner that the front side of the third wafer is opposed to the back side of the second wafer and that the electrodes of the third wafer are respectively bonded to the electrodes of the second wafer, and a second back grinding step of grinding the back side of the third wafer to expose each kerf of the third wafer to the back side of the third wafer.

REFERENCES:
patent: 7608481 (2009-10-01), Masuda
patent: 7622366 (2009-11-01), Nakamura
patent: 2007/0218593 (2007-09-01), Masuda
patent: 2009/0218593 (2009-09-01), Kamikawa et al.
patent: A 60-206058 (1985-10-01), None

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