Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
2006-04-04
2006-04-04
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
C365S046000, C365S063000, C365S066000, C365S158000, C365S100000
Reexamination Certificate
active
07023743
ABSTRACT:
This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.
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Nejad Hasan
Seyyedy Mirmajid
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
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