Stacked CMOS SRAM cell with polysilicon transistor load

Details Stacked CMOS SRAM cell with polysilicon transistor load Stacked CMOS SRAM cell with polysilicon transistor load

1991-06-03

1994-03-29

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 67, 257377, 257382, 257385, 257388, 437 48, 437 49, 437 62, 437191, 437208, 437915, H01L 2701, H01L 21265

Patent

active

052987825

ABSTRACT:
A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.

REFERENCES:
patent: 4502202 (1985-03-01), Malhi
patent: 4710897 (1987-12-01), Masuoka et al.
patent: 4777147 (1988-10-01), Scott et al.
patent: 4814850 (1989-03-01), Malhi
patent: 4890148 (1989-12-01), Ikeda et al.
patent: 4950619 (1990-08-01), Yoon et al.
patent: 5057898 (1991-10-01), Adan et al.

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