Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-08-25
2002-04-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S698000, C257S723000
Reexamination Certificate
active
06365963
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a stacked-chip semiconductor device and, more particularly, to the structure of the stacked-chip semiconductor device having a smaller thickness.
(b) Description of the Related Art
With development of higher functions of the electronic device, demand for higher integration of semiconductor elements constituting the electronic device has increased. For achievement of the higher integration, it may be considered preferable that a plurality of ICs, such as including a logic IC and a memory IC, be integrated on a single chip. However, this type of integration complicates the fabrication process as well as the electric tests of the chip, to thereby raise the costs of the electronic device. Thus, it is usual that a plurality of chips, typically two chips, be stacked in a single package for a higher integration without raising the costs.
FIG. 1
shows a conventional stacked-chip structure of a semiconductor device wherein a first semiconductor chip (first chip)
202
is mounted on a packaging board
201
and then a second chip
203
is stacked onto the first chip
202
with an intervention of an adhesive insulator layer disposed therebetween. The first chip
202
is generally larger than the second chip
203
in the planar dimensions. Bonding wires
204
made of gold (Au) connect the chip electrodes of the first and second chips
202
and
203
and the internal electrode pads
206
formed on the top surface of the packaging board
201
. Mold resin
205
encapsulates the entire chips
202
and
203
and the bonding wires
204
for protection against mechanical damages or contamination.
The bottom surface of the packaging board
201
mounts thereon external electrode pads
208
connected to the internal electrode pads
206
by wiring layer
207
. A solder ball
209
is formed on each external electrode pad
208
, and used for mounting the stacked-chip semiconductor device on a mounting board not shown in the figure.
In the structure shown in
FIG. 1
, there is a restriction in which the underlying first chip
202
must be larger than the overlying second chip
203
. Otherwise, an overhang state of the overlying second chip
203
is subjected to damages during the wire bonding step for the chips
202
and
203
due to a pressure rise caused by the wire bonding process.
In addition, the overall height or thickness of the semiconductor device is undesirably large due to the combination of the stacked-chip structure and the location of the external solder bumps
209
.
FIG. 2
shows another conventional stacked-chip structure of a semiconductor device, wherein the first chip
303
is mounted on a packaging board
301
in a depression
302
formed in the packaging board
301
, and the second chip
307
is stacked onto the first chip
303
with an intervention of resin
306
disposed therebetween. The resin
306
is also filled in the depression
302
around the first chip
303
. The second chip
307
is larger than the first chip
301
and the depression
302
, and thus the second chip
307
is mounted on the top surface of the packaging board
301
above the first chip
301
.
The first chip
303
is mounted by a flip-chip bonding technique using internal electrode pads
304
formed on the bottom of the depression
302
and Au bumps
305
formed on the first chip
303
. The second chip
307
is also mounted by a flip-chip bonding technique using internal electrode pads
308
formed on the top surface of the packaging board
301
and Au bumps
309
formed on the second chip
307
. External electrode pads
311
are formed on the peripheral area of the top surface of the packaging board
301
, and solder balls
312
are formed on the external electrode pads
311
.
In the conventional device of
FIG. 2
, there is an advantage in that the overall height of the stacked structure is reduced compared to the conventional device of FIG.
1
. However, the process for forming the depression
302
by counterboring on the packaging board
301
raises the cost of the packaging board
301
. In addition, the depression
302
also reduces the mechanical strength of the packaging board
301
and may cause a warp of the packaging board
301
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a new stacked-chip structure of a semiconductor device, which is capable of reducing the height or thickness of the semiconductor device.
The present invention provides a stacked-chip semiconductor device including a rigid insulator board having a first wiring pattern formed on a top surface thereof and an opening formed therein, a base insulator film having a top surface bonded onto a bottom surface of the rigid insulator board, the top surface of the base insulator film mounting thereon a second wiring pattern electrically connected to the first wiring pattern, a first semiconductor chip mounted on the top surface of the base insulator film and received in the opening, the first semiconductor chip having chip electrodes electrically connected to the second wiring pattern, and a second chip mounted on the rigid insulator board overlying the opening and chip electrodes connected to the first wiring pattern, the first wiring pattern including external electrode pads.
In accordance with the stacked-chip semiconductor device of the present invention, the combination of the rigid insulator board and the base insulator film affords a smaller thickness of the semiconductor device substantially without reducing the overall mechanical strength of the semiconductor device.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 5808878 (1998-09-01), Saito et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 6181008 (2001-01-01), Avery et al.
patent: 2-126685 (1990-05-01), None
patent: 5-129516 (1993-05-01), None
Clark Sheila V.
Laff, Whitesel & Saret, Ltd.
Michael Best & Friedrich LLC
Whitesel J. Warren
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