Stacked chip scale package structure

Details Stacked chip scale package structure Stacked chip scale package structure

2002-06-06

2003-10-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S723000, C257S778000

Reexamination Certificate

active

06633086

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit (IC) package and, more particularly, to an improved chip stacked structure of stacked chip size/scale package (stacked CSP).
BACKGROUND OF THE INVENTION
As shown in
FIGS. 1 and 2
, in a chip stacked structure of stacked chip size/scale package (stacked CSP, or called multi-chip package, MCP), a lower chip
12
and an upper chip
14
are disposed on a substrate
10
. Each interface is bonded together with adhesives
16
and
18
. Gold wires
20
are used to connect bonding pads
22
and
24
on the upper and lower chips
14
and
12
to contacts
26
on the substrate
10
. A plurality of solder balls
28
are provided below the substrate
10
.
In the prior art, the size of the lower chip is larger than that of the upper chip so as to limit the layout of the substrate. Even the size of the upper chip is larger than that of the lower chip, as shown in
FIG. 3
, in order to let the wire path be the shortest, the bonding pads of the upper and lower chips
14
and
12
are arranged in the same direction, and the upper chip
14
can be larger than that of the lower chip
12
only in the direction without any bonding pad. However, because bonding pads
30
,
32
,
34
, and
36
are suspended, wire bonding cannot be performed. This is because a chip of stacked CSP is very thin, wire bonding of suspended chip will certainly result in die crack. This problem causes that existent chip design has not widespread application, and sometimes the direction of the upper chip cannot be adjusted due to layout difficulty of the substrate.
Accordingly, the present invention proposes a chip stacked structure of stacked CSP to resolve the problems in the prior art.
SUMMARY AND OBJECTS OF THE PRESENT INVENTION
The primary object of the present invention is to provide a package structure having dummy die design to resolve the problem of die crack caused by wire bonding of suspended chip.
Another object of the present invention is to provide a multi-layer CSP structure capable of flexibly adjusting the size and installation direction of the upper chip.
Yet another object of the present invention is to provide a package structure capable of shortening the trace length on the substrate to enhance the electric performance thereof.
According to the present invention, in a stacked CSP structure, an upper chip is disposed on a lower chip. The size of the upper chip can be larger than that of the lower chip. At least a dummy die is disposed below the suspended portion of the upper chip as a support during wire bonding. The dummy die has a thickness commensurate with that of the lower chip. A gap is reserved between the dummy die and the lower chip.


REFERENCES:
patent: 6215193 (2001-04-01), Tao et al.
patent: 6337226 (2002-01-01), Symons
patent: 6448659 (2002-09-01), Lee
patent: 6461897 (2002-10-01), Lin et al.

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