Stacked chip package with redistribution lines

Details Stacked chip package with redistribution lines Stacked chip package with redistribution lines

2011-07-05

2011-07-05

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257S698000, C257S784000, C257SE25006, C257SE25010, C257SE25011, C257SE25013, C257SE25020, C257SE25023, C257SE25027, C257SE23085

Reexamination Certificate

active

07973401

ABSTRACT:
A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

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