Stacked chip package and method for forming the same

Details Stacked chip package and method for forming the same Stacked chip package and method for forming the same

2007-01-15

2009-12-29

Thai, Luan C (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S777000, C257S686000, C257SE27137, C257SE27144, C257SE27161

Reexamination Certificate

active

07638365

ABSTRACT:
Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

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English language abstract of Korean Publication No. 10-2001-0083204.
English language abstract of Korean Publication No. 10-2002-0028474.
English language abstract of Japanese Publication No. 2004-63569.

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