Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-16
2002-05-07
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S305000, C257S386000
Reexamination Certificate
active
06384443
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked capacitor in which a high-dielectric constant material is used in a dielectric film, as well as a method of manufacturing the same.
2. Description of the Background Art
A DRAM (dynamic random access memory) is generally composed of a memory array block that is a storage area for storing a plenty of memory data, and a peripheral circuit block needed in handling input/output operation to the exterior. In the memory array block occupying a large area on a semiconductor chip, a plurality of memory cells storing unit memory data are disposed in a matrix.
A single memory cell is generally composed of one MOS transistor and one capacitor connected thereto. This memory cell is called “one-transistor one-capacitor type memory cell.” This type of memory cell has a simple configuration, thereby making it easy to improve the integration degree of a memory array. Therefore it has found wide use in mass DRAMs.
There are various types of capacitors, for example, a so-called stacked capacitor type. The stacked capacitor has the feature that the opposed-surface area between the capacitor electrodes is increased by allowing the electrode and dielectric film of the capacitor to extend above a field oxide film and above the gate electrode of a transistor. Since the stacked capacitor has this feature, it is easy to ensure the electrostatic capacity of the capacitor even when the scale down of elements is advanced with integration of semiconductor memory. Thus, the stacked capacitor has come into increasing use due to high integration of semiconductor memory.
When the scale down of elements is advanced, it requires that a stacked capacitor is made high for ensuring the opposed surface area between electrodes while minimizing its lateral extending. In its present state of a significant advancement of scale down, however, it is going to be no longer capable of securing a predetermined electrostatic capacity by such a method of improving the structure. This is true for trench capacitors and cylindrical capacitors which are of other typical three-dimensional capacitor structure.
Upon this, in order to increase the electrostatic capacity of capacitors, some attempts have been made to employ, as a dielectric film, a high-dielectric constant material such as BST (barium strontium titanate).
FIG. 19
is a cross section illustrating a capacitor part of a DRAM memory cell in which a high-dielectric constant material, e.g., BST, is used as a dielectric film.
Referring to
FIG. 19
, a dielectric film
8
composed of a high-dielectric constant material is sandwiched by an upper electrode
9
, lower electrode
5
D and sidewall lower electrode
7
D. The lower electrode
5
D is connected to a conductive plug
3
via a barrier metal
13
. The conductive plug
3
extends through an interlayer insulting film
2
and makes connection with the top surface of a semiconductor substrate
1
. An interlayer insulating film
10
is disposed on the upper electrode
9
. The dielectric film
8
, upper electrode
9
, barrier metal
13
, lower electrode
5
D and sidewall lower electrode
7
D are insulated from the semiconductor substrate
1
by the interlayer insulating film
2
. These components as described constitute a stacked capacitor.
For instance, platinum is used for the upper electrode
9
, lower electrode
5
D and sidewall lower electrode
7
D, and titanium nitride is used for the barrier metal
13
. The interlayer insulating films
2
and
10
are formed of a silicon oxide film or the like. The dielectric film
8
composed of a high-dielectric constant material, e.g., BST, is formed by means of reactive sputtering, CVD (chemical vapor deposition), or the like.
A transistor and an element isolation region comprising a silicon oxide film or the like, which are not shown in
FIG. 19
, are disposed on the top surface of the semiconductor substrate
1
. Aluminum wiring, which is also not shown, is disposed above the stacked capacitor.
In the capacitor of conventional memory cells of a DRAM, polycrystalline silicon is used for upper and lower electrodes, and a silicon oxide film obtained by the thermal oxidation of silicon, or a silicon nitride film formed by CVD method, is used as a dielectric film. All of these films are of a silicon compound, and are easily formed on the lower electrode composed of polycrystalline silicon.
If an attempt were made to apply a dielectric film composed of BST to a conventional capacitor structure so that it is formed on a lower electrode composed of polycrystalline silicon, the polycrystalline silicon that is electrochemically base is easily oxidized with the oxygen atoms of the BST. As a result, a silicon oxide film is formed at the interface of the dielectric film and lower electrode. Since the silicon oxide film has a low dielectric constant, it nullifies the effect of the high-dielectric constant material, which causes a substantial reduction in the electrostatic capacity of the capacitor and also raises the resistance value of the polycrystalline silicon as the lower electrode. These problems also occur in the upper electrode.
Therefore, when a high-dielectric constant material, e.g., BST, is used for a dielectric film, a noble metal that is electrochemically noble and has strong oxidation resistance is used for upper and lower electrodes. Examples of the noble metal are platinum, iridium and palladium. For this reason, platinum is exemplified as the material of the upper electrode
9
, lower electrode
5
D and sidewall lower electrode
7
D in the stacked capacitor shown in FIG.
19
. The sidewall lower electrode
7
D is provided in order to avoid that the barrier metal
13
makes a direct contact with the dielectric film
8
to cause a chemical reaction.
In the stacked capacitor of
FIG. 19
, when a material composed of silicon, e.g., polycrystalline silicon, is used for the conductive plug
3
, unless the barrier metal
13
is present, silicidation might take place between the lower electrode
5
D and conductive plug
3
, resulting in an increase in resistance value. In addition, the oxygen atoms which departed from the dielectric film
8
or the like, and then penetrated the lower electrode
5
D, may reach the conducive plug
3
and semiconductor substrate
1
, thereby oxidizing them. It is therefore necessary to dispose a conductive barrier metal between the lower electrode
5
D and conductive plug
3
, by which the element diffusion therebetween is suppressed. The barrier metal
13
of
FIG. 19
is provided for this reason.
In a conventional stacked capacitor employing a dielectric film composed of a high-dielectric constant material, a lower electrode
5
D is shaped by dry etching.
FIG. 20
is a cross section illustrating a step in the course of manufacturing the lower electrode
5
D.
FIG. 20
shows the state that, by using a patterned resist
12
as a mask, the lower electrode
5
D is subjected to a dry etching, thereafter, a barrier metal
13
is also subjected to a dry etching.
When a noble metal, e.g., platinum, is employed as a lower electrode
5
D, the dry etching of the lower electrode
5
D causes the problem that the etched noble metal particles tend to redeposit on the side surfaces of a resist
12
and the lower electrode
5
D. For this reason, in
FIG. 20
, redeposit
14
is present on the side surfaces of the resist
12
and the lower electrode
5
D.
Therefore, the pattern size b of the lower electrode
5
D and barrier metal
13
to be provided after etching is greater than the pattern size a of the resist. This tendency increases with greater thickness of the lower electrode
5
D to be etched. That is, the pattern size according to design cannot be achieved, which requires some corrective actions such that allowance should be made in the design of a circuit pattern, resulting in a tedious work.
Thus, a noble metal such as platinum has the advantage of being chemically stable, while it has the disadvantage of having difficulties in dry etching. It becomes therefore more d
Mitsubishi Denki & Kabushiki Kaisha
Rao Shrinivas H.
Weiss Howard
LandOfFree
Stacked capacitor and method of manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked capacitor and method of manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked capacitor and method of manufacturing same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2836562