Stacked bottom lead package in semiconductor devices and fabrica

Details Stacked bottom lead package in semiconductor devices and fabrica Stacked bottom lead package in semiconductor devices and fabrica

1997-11-19

2000-02-29

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

438106, 438121, H01L 2144, H01L 2148, H01L 2150

Patent

active

060308583

ABSTRACT:
The present invention relates to a stacked bottom lead package in semiconductor devices and a method thereof. More specifically, comprising leads that are bent along with the circumference of the body which has been premolded, wherein a chip is include inside the premolded body. The package and the method thereof according to the present invention enable a dual process, decreasing solder fatigue of the lead by carrying heat via the extended leads and emitting the heat out of the chip, and decreasing the area required for stacking semiconductor packages.

REFERENCES:
patent: 4553420 (1985-11-01), Fierkens et al.
patent: 5363279 (1994-11-01), Cha
patent: 5446620 (1995-08-01), Burns et al.
patent: 5801439 (1998-09-01), Fujisawa et al.

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