Stacked bit line dual word line nonvolatile memory

Details Stacked bit line dual word line nonvolatile memory Stacked bit line dual word line nonvolatile memory

2005-08-31

2008-09-02

Lee, Calvin (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S131000

Reexamination Certificate

active

07420242

ABSTRACT:
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

REFERENCES:
patent: 4489478 (1984-12-01), Sakurai
patent: 5441907 (1995-08-01), Sung et al.
patent: 5536968 (1996-07-01), Crafts et al.
patent: 5565703 (1996-10-01), Chang
patent: 5835396 (1998-11-01), Zhang
patent: 6021079 (2000-02-01), Worley
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6768661 (2004-07-01), Vyvoda et al.

Affiliated with

Also associated with

Rating

Stacked bit line dual word line nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked bit line dual word line nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked bit line dual word line nonvolatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3988161