Stackable single package and stacked multi-chip assembly

Details Stackable single package and stacked multi-chip assembly Stackable single package and stacked multi-chip assembly

2007-09-04

2007-09-04

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S686000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE23085, C257SE25029, C438S109000

Reexamination Certificate

active

11204281

ABSTRACT:
A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.

REFERENCES:
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patent: 6750545 (2004-06-01), Lee et al.
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patent: 102 01 204 (2003-07-01), None
patent: 102 51 530 (2004-05-01), None

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