Stackable semiconductor package

Details Stackable semiconductor package Stackable semiconductor package

2008-11-05

2010-06-15

Zarneke, David A (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S692000, C257S773000, C257S777000, C257SE23008, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257S698000

Reexamination Certificate

active

07737542

ABSTRACT:
A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are ref lowed and fused together.

REFERENCES:
patent: 6987314 (2006-01-01), Yoshida et al.
patent: 7459349 (2008-12-01), Yoshida et al.
Akito Yoshida et al., “Design and Stacking of An Extremely Thin Chip-Scale Package”,Electronic Components and Technology Conference, May 27-30, 2003, IEEE, pp. 1095-1100.

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