Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-01-18
2001-11-20
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S787000, C257S686000, C257S685000
Reexamination Certificate
active
06320251
ABSTRACT:
FIELD OF THE INVENTION
The present application concerns a package for one or more electronic devices (e.g., integrated circuits), and in particular, a package that easily can be electrically interconnected with other similar packages.
BACKGROUND OF THE INVENTION
In the field of integrated circuit packaging, it is known to include a plurality of integrated circuits in a single package body. Bond pads of each integrated circuit are electrically connected by bond wires to leads of the package. The leads are subsequently electrically connected to metal traces on a printed circuit board upon which the package is mounted. Providing a plurality of integrated circuits in one package allows an increase in package density without a significant increase in the area of the printed circuit board that is consumed by the package.
A problem with conventional packages, even packages that contain a plurality of integrated circuits, is that further increases in density per unit area of the printed circuit board are not easily attainable. So, for example, if a package includes two sixteen megabit memory integrated circuits (total thirty-two megabits), then increasing the total amount of memory to 128 megabits would require three additional packages, each of which would require additional mounting area on the printed circuit board.
One known method to increase package density is to mount a first small outline integrated circuit package (“SOIC”) having either gull wing or J lead styles on a printed circuit board. The leads are soldered to metal traces on the printed circuit board. Next, the leads of a second SOIC package are cut in length so as to form lead stubs. The second SOIC package is then stacked on top of the first SOIC package, and the lead stubs of the second SOIC package are soldered to the lead stubs of the first SOIC package. This arrangement has obvious shortcomings. First, SOIC packages tend to be thick and much larger rather than the integrated circuit. Thus, a stack of two SOIC packages will have a large footprint and will extend rather high above the printed circuit board. Second, SOIC packages are not meant to be stacked. It is difficult and time consuming to cut the leads of the second SOIC and then solder the cut leads to the leads of the first SOIC. Third, only two SOIC packages can typically be stacked in this manner due to the size of the SOIC packages and the leads. Finally, the footprint of the first SOIC package on the printed circuit board is relatively large due to the gull wing or J-style leads.
SUMMARY OF THE INVENTION
The present invention allows an increase in the density of integrated circuit or other electronic device packages on a printed circuit board without a corresponding increase in the area of the printed circuit board consumed thereby. In addition, the packages of the present invention allow flexibility in determining how many packages to include in a given area of the printed circuit board. For example, packages made in accordance with one embodiment of the present invention may include one or more memory devices. The packages are made so that they can be stacked one on top of the other so as to form a stack of electrically interconnected packages. Accordingly, the size of the memory can be varied by varying the number of packages stacked together. The packages also may be placed side by side on the printed circuit board so that their leads abut. In this manner, adjacent packages and adjacent stacks of packages can be electrically interconnected. Another advantage of the present invention is that the packages may be made very thin (e.g., about 0.5 mm), and near-chip size. Thus, the packages can be densely mounted in small areas of a printed board.
In one embodiment, a package within the present invention includes a package body formed of a molded encapsulant material. The package body includes a first surface, an opposite second surface, and peripheral side surfaces extending vertically between the first surface and the second surface. Within the package body is a planar die pad upon which an integrated circuit device is mounted. Leads extend from a first end that is within the package body and is adjacent to the die pad to a second end outside of the package body. A surface of each lead is exposed at the second surface of the package body. The portion of each lead that extends outside the package body is bent so that the lead extends vertically along the side surface of the package and horizontally over the first surface of the package. The leads thus have a C-shape. The packages may be stacked one on top of the other so that the leads of a lower package will abut the leads of an upper package stacked on the lower package so that the two packages may be electrically interconnected. Alternatively, one package may be placed next to another on a printed circuit board so that the vertically extending portions of the leads of adjacent packages are juxtaposed for electrical interconnection.
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Amkor Technology Inc.
Clark Jhihan B
Parsons James E.
Skjerven Morrill & MacPherson LLP
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