Stackable layers containing encapsulated chips

Details Stackable layers containing encapsulated chips Stackable layers containing encapsulated chips

1999-03-31

2000-09-12

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making point contact device

438113, 438127, 438460, H01L 2144, H01L 2148, H01L 2150

Patent

active

061177040

ABSTRACT:
A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.

REFERENCES:
patent: 5478781 (1995-12-01), Bertin et al.
patent: 5952725 (1999-09-01), Ball

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