Stack package made of chip scale packages

Details Stack package made of chip scale packages Stack package made of chip scale packages

2008-12-18

2010-11-30

Thai, Luan C (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S678000, C257S688000, C257S780000, C257SE25013

Reexamination Certificate

active

07843053

ABSTRACT:
A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

REFERENCES:
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patent: 6876074 (2005-04-01), Kim
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patent: 2004/0124518 (2004-07-01), Karnezos
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patent: 2005/0051903 (2005-03-01), Ellsberry et al.
patent: 2000-216327 (2000-08-01), None
patent: 2001-0011310 (2001-02-01), None
patent: 2001-0028845 (2001-04-01), None
English language abstract of Japanese Publication No. 2000-216327.
English language abstract of Korean Publication No. 2001-0011310.
English language abstract of Korean Publication No. 2001-0028845.

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