Stack package having pattern die redistribution

Details Stack package having pattern die redistribution Stack package having pattern die redistribution

2006-12-29

2010-11-16

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257SE25013

Reexamination Certificate

active

07834463

ABSTRACT:
A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.

REFERENCES:
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6812575 (2004-11-01), Furusawa
patent: 6979905 (2005-12-01), Nishida et al.
patent: 7327038 (2008-02-01), Kwon et al.
patent: 2006/0267173 (2006-11-01), Takiar et al.
patent: 1020040070020 (2004-08-01), None

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