Stack package and stack packaging method

Details Stack package and stack packaging method Stack package and stack packaging method

2011-01-04

2011-01-04

Cao, Phat X (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S686000, C257SE23085

Reexamination Certificate

active

07863715

ABSTRACT:
Provided are a stack package and a stack packaging method. The stack package includes: a first package; and a second package stacked on the first package, wherein external leads of the first package and the second package are directly connected to one another and inner leads thereof are arranged in different shapes so that the Chip Select signal of the second package are input through a No Select pin of the first package.

REFERENCES:
patent: 2008/0246134 (2008-10-01), Szewerenko et al.
patent: 09-036297 (1997-02-01), None
patent: 2002-0082543 (2002-10-01), None
patent: 2003-0029681 (2003-04-01), None
patent: 2003-0046933 (2003-06-01), None
English language abstract of Japanese Publication No. 09-036297.
English language abstract of Korean Publication No. 2002-0082543.
English language abstract of Korean Publication No. 2003-0029681.

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