Stack gate with tip vertical memory and method for...

Details Stack gate with tip vertical memory and method for... Stack gate with tip vertical memory and method for...

2005-03-22

2005-03-22

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S323000, C257S326000

Reexamination Certificate

active

06870216

ABSTRACT:
A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

REFERENCES:
patent: 5828602 (1998-10-01), Wong
patent: 20040057328 (2004-03-01), Lin et al.

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