Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-01
2000-10-10
Peikari, B. James
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711110, 711109, 710 53, 710 56, 710 57, G06F 1212
Patent
active
061311448
ABSTRACT:
The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow. If an underflow occurs during a context switch the overflow/underflow unit resolves the underflow by spilling a plurality of data word from the stack cache to the stack and equating the bottom pointer to the optop pointer. If an underflow without a context switch the overflow/underflow unit resolves the underflow by equating the bottom pointer to the optop pointer.
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Gunnison Forrest
Peikari B. James
Sun Microsystems Inc.
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