Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-07-12
2002-05-14
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S157000, C331S014000, C331S017000
Reexamination Certificate
active
06389092
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to electronic circuits, and more particularly the invention relates to phase locked loop circuits. A phase locked loop (PLL) is commonly used in many electronics applications to maintain a fixed phase relationship between an input (e.g., clock) signal and a reference signal. A phase locked loop designed for a digital application typically includes a phase and/or frequency detector, a charge pump, a loop filter, a VCO, and an (optional) divider. The phase detector determines the phase differences between an input signal (i.e., an input data stream or an input clock) and a reference signal derived from the VCO, and generates a detector output signal indicative of the detected phase differences. The charge pump receives the detector output signal and generates a set of phase error signals (e.g., UP and DOWN). The loop filter filters the phase error signals to generate a control signal that is then used to adjust the frequency of the VCO such that the frequencies of the two signals provided to the phase detector are locked.
FIG. 1
is a block diagram of a conventional phase locked loop
100
. An input signal is provided to a phase detector
110
that also receives a reference signal from a divider
123
. The input signal can be a clock signal, a data stream, or some other types of signal having phase and/or frequency information to which the phase locked loop can locked. The reference signal is typically a clock signal used to trigger the phase detector. Phase detector
110
generates an output signal PDOUT indicative of the timing differences (i.e., the phase differences) between the input signal and the reference signal. The PDOUT signal is provided to a charge pump
114
that generates an output signal CPOUT indicative of the detected phase error between the input and reference signals. In some designs, the PDOUT signal is logic high if the phase of the input signal is early (or late) relative to that of the reference signal, logic low if the phase of the input signal is late (or early) relative to that of the reference signal, and tri-stated for a period of time between clock edges.
The CPOUT signal is provided to a loop filter
120
that filters the signal with a particular transfer characteristic to generate a control signal. The control signal is then provided to, and used to control the frequency of, a voltage-controlled oscillator (VCO)
122
. VCO
122
generates an output clock CLK_OUT having a frequency that is locked to that of the input signal (when the phase locked loop is locked). The output clock is provided to divider
123
that divides the frequency of the output clock by a factor of N to generate the reference signal. Divider
123
is optional and not used when the frequency of the output clock is the same as that of the input signal (i.e., N=1). The control signal adjusts the frequency of VCO
122
such that the frequencies of the two signals provided to phase detector
110
are locked.
The charge pump typically requires an input signal having rail-to-rail signal swing and sharp edges. Signals meeting these requirements can be readily provided by a phase detector at (relatively) low operating frequencies. However, at higher frequencies (e.g., 2.488 GHz for a SONET OC-48 transceiver), it is difficult to design a phase detector having rail-to-rail signal swing and sharp edges. To provide the required signal characteristics, the phase detector would typically need to be designed using a combination of large die area and large amounts of bias current. Besides the design challenge for such phase detector, the rail-to-rail signal swing and sharp edges generate large amounts of noise that can degrade the performance of the phase locked loop and other nearby circuits.
The present invention is directed to improving the stability of a phase locked loop circuit.
SUMMARY OF THE INVENTION
Briefly, and in accordance with the invention, a pole associated with a loop filter is separated and placed after a phase detector and before a signal processing circuit such as a charge pump or transconductance amplifier. Thus, changes in filter resistance for “fast lock” acquisition or for “normal” operation do not affect the circuit pole. The ratio of loop bandwidth, W
0
to circuit pole Wp
1
, varies only linearly, thus making the phase locked loop more stable during the bandwidth adjustment.
The invention and objects and features thereof will be more readily apparent from the following description and appended claims when taken with the drawings.
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NewPort Communications, Inc.
Townsend and Townsend / and Crew LLP
Tse Young T.
Woodward Henry K.
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