Stable memory cell

Details Stable memory cell Stable memory cell

2006-03-07

2006-03-07

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S194000, C365S189040

Reexamination Certificate

active

07009871

ABSTRACT:
Systems and methods for improving the stability of memory cells. One embodiment comprises an SRAM cell which includes a first data node switchably coupled to a first bit line and a second data node switchably coupled to a second bit line. The SRAM cell is configured to be read by coupling the first data node to the first bit line and coupling the second data node to the second bit line to enable a low voltage at one of the data nodes to pull down the corresponding bit line. One of the bit lines in the memory cell is switchably coupled to a low voltage so that, when the memory cell is read, this bit line is coupled to the low voltage when the voltage at the opposing data node is high and decoupled from the low voltage when the voltage at the opposing data node is low.

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Bernstein et al;SOI circuit Design Concepts; Chapter 8.7; Kluwer Academic Publishers.

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