Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-07
2004-10-12
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S133000, C257S205000, C257S273000, C257S337000, C257S350000, C257S370000, C257S511000, C438S135000, C438S202000, C438S205000, C438S234000, C438S309000
Reexamination Certificate
active
06803634
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-341906 filed on Nov. 7, 2001.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a CMOSFET and a bipolar transistor and to a method for manufacturing the semiconductor device. In the method, the bipolar transistor is formed by taking advantage of steps for forming a well region, source regions, and drain regions of the CMOSFET.
With a manufacturing process for a semiconductor device called a Bi-CMOS IC, in which bipolar transistors and CMOSFETs are formed on the same substrate, there is a technology for forming, for example, base regions of the bipolar transistors using diffusion regions for forming wells for the CMOSFETs and for forming emitter regions using diffusion regions for forming the source and drain regions in order to reduce the number of process steps. In a semiconductor device
1
shown in
FIG. 24
, a silicon-on-insulator (SOI) substrate is included, and a CMOSFET
4
and a bipolar transistor
5
are located over an insulating film
3
on a silicon substrate
2
.
An SOI layer included in the SOI substrate includes a high impurity concentration n-type silicon layer
6
and a low impurity concentration n-type silicon layer
7
on the insulating film
3
, and the transistors
4
,
5
of the device
1
are isolated by trenches
8
and by LOCOS
9
in a surface of the device
1
. The CMOSFET
4
includes p channel-type and n channel-type MOSFETs
4
a
,
4
b
, in which an n-type well
10
and a p-type well
11
are included, respectively. Source and drain regions
12
,
13
are included in the n-type well
10
and the p-type well
11
, respectively. Each gate electrode
15
is located on a gate oxide film
14
. Contact holes are located in an insulating film
16
. Aluminum electrodes
17
are in electric contact with the source and drain regions
12
,
13
.
An npn transistor
5
includes a low impurity concentration n-type silicon layer
7
as a collector region, in a surface of which a p-type base region
18
is located. An n-type emitter region
19
and a base contact region
20
are located in a surface of the p-type base region
18
. A collector contact region
21
is also located in the surface of the silicon layer
7
.
The semiconductor device
1
is formed by the following process flow, which is shown in
FIGS. 25A
to
25
G. As shown in
FIG. 25A
, an SOI substrate
210
, in which n-type single crystal silicon layers
6
,
7
are located on an insulating layer
3
, is prepared. Then, trenches
8
are formed outside the areas where for transistors
4
,
5
are formed, as shown in FIG.
25
B. Then, wells
10
,
11
are formed using a known CMOSFET process. Simultaneously, base region
18
is formed, as shown in FIG.
25
C. Next, as shown in
FIG. 25D
, LOCOS
9
are formed, and a gate oxide film
14
and gate electrodes
15
are formed, as shown in FIG.
25
F.
Using the gate electrodes
15
as a mask, the source and drain regions
12
,
13
of MOSFETs
4
a
,
4
b
are formed, as shown FIG.
25
F. Simultaneously, an emitter region
19
, a base contact region
20
, and a collector contact region
21
are formed. Finally, an insulating film
16
and the aluminum electrodes
17
are formed to complete a Bi-CMOSFET semiconductor device
1
.
Because the npn transistor
5
is formed using a CMOSFET manufacturing process, the Bi-CMOSFET semiconductor device
1
has the following drawback with the characteristics of the npn transistor
5
. The base region
18
of the transistor
5
is simultaneously formed at the step for forming the p-type well
11
, so the surface impurity concentration of the base region
18
is generally relatively low. Therefore, the characteristics of the transistor
5
can shift due to a slight shift in the amount of charges at the interface between the p-type base region
18
and the insulating film
16
, which is made of SiO
2
, under a certain biasing condition for driving the transistor
5
. The interface is shown with small x-marks in FIG.
24
. As a result, the characteristics of the transistor
5
become unstable, and operating errors are caused in some circuit designs.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above aspects. A first object of the present invention is to provide a semiconductor device that is relatively stable in the device characteristics, which are affected by the impurity concentration at a surface of a base region, even when a bipolar transistor and a CMOSFET is simultaneously formed in a device using a CMOSFET process. A second object is to provide a method of manufacturing the semiconductor device.
In the present invention, a CMOSFET and a bipolar transistor are formed into a single unit on a substrate. The steps for forming a well region, source regions, and drain regions of the CMOSFETs are also used for forming the bipolar transistors, and one of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration area in the surface.
Alternatively, the surface of the base region is exposed by ultraviolet rays in order to reduce the amount of charges at the interface between the base region and an insulating film located on the surface of the base region.
Alternatively, after an insulating film is formed at the surface of the base region of the bipolar transistor, a hydrogen barrier film is formed such that the hydrogen barrier film covers the surface of the base region.
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patent: 5340756 (1994-08-01), Nagayasu
patent: 6156595 (2000-12-01), Sawada
patent: 6352887 (2002-03-01), Hutter et al.
patent: 6365932 (2002-04-01), Kouno et al.
patent: 6492211 (2002-12-01), Divakaruni et al.
patent: 0948046 (1999-10-01), None
patent: 948046 a1 (1999-10-01), None
patent: A-60-144962 (1985-07-01), None
patent: A-2-100339 (1990-04-01), None
Terashima, Tomohide; Yamamoto, Fumitoshi; Hatasako, Kenichi; and Hine, Shiro; “Development of a 0.5&mgr;m BiCMOS and DMOS process,” EDD-99-108, Spe.-99-88. pp. 87-92.
Kanemaru Toshitaka
Mizuno Shoji
Okuno Takuya
Denso Corporation
Huynh Andy
Nelms David
Posz & Bethards, PLC
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