SRAM with stacked capacitor spaced from gate electrodes

Details SRAM with stacked capacitor spaced from gate electrodes SRAM with stacked capacitor spaced from gate electrodes

1996-07-17

1998-07-14

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257379, 257903, 365 63, 365154, 365156, 365205, 365207, H01L 2711, H01L 2362, G11C 1100, G11C 700

Patent

active

057809100

ABSTRACT:
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

REFERENCES:
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5631863 (1997-05-01), Fechner et al.
patent: 5635731 (1997-06-01), Ashida
patent: 5652457 (1997-07-01), Ikeda et al.

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