SRAM with small planar layout

Details SRAM with small planar layout SRAM with small planar layout

1994-09-21

1996-01-23

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257755, 257904, 257915, 365154, H01L 2711

Patent

active

054867177

ABSTRACT:
A memory cell region is provided with a pair of driver transistors as well as a pair of access transistors. Each of the access transistors is formed of a field effect transistor having a gate electrode layer. An insulating layer is formed over the driver transistors and access transistors, and is provided with contact holes located within the memory cell region and reaching the gate electrode layers. Conductive layers are formed on the insulating layer, and are in contact with the gate electrode layers through the contact holes. Thereby, a memory cell structure of an SRAM has a small planar layout area and thus is suitable to high integration.

REFERENCES:
patent: 5005068 (1991-04-01), Ikeda et al.
patent: 5239196 (1993-08-01), Ikeda et al.
patent: 5436506 (1995-07-01), Kim et al.
"A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", Tomohisa Wada et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 727-732.
"A 20ns 64K NMOS RAM", S. SChuster et al., 1984 IEEE International Solid-STate Circuits Conference Digest of Technical Papers, pp. 226-227.

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