SRAM with programmable preset data

Details SRAM with programmable preset data SRAM with programmable preset data

1993-05-03

1995-08-08

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

For complementary information

365202, 365203, G11C 11413

Patent

active

054405130

ABSTRACT:
A static random access memory (20) with programmable preset data includes two bit line pairs for each column of memory cells (31-36). In response to a control signal during a programming cycle, preset programming logic (28) charges one of the bit line pairs of each column of memory cells to a predetermined logic state and the other bit line pair to a logical complement of the predetermined logic state. Memory cells (31-36) of each column of memory cells are coupled to either one of the two bit line pairs by mask programming. During the programming cycle, each of the memory cells (31-36) store programmed data depending upon which bit line pair each memory cell is coupled to. The memory (20) provides the advantages of a static random access memory and the nonvolatility of a read only memory.

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patent: 4899317 (1990-02-01), Hoekstra et al.
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patent: 4995004 (1991-02-01), Lee
patent: 5040143 (1991-08-01), Matsumura et al.
patent: 5189641 (1993-02-01), Arakawa
patent: 5197029 (1993-03-01), Schreck et al.
patent: 5233561 (1993-08-01), Mori et al.
patent: 5287485 (1994-02-01), Umina et al.

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