SRAM with forward body biasing to improve read cell stability

Details SRAM with forward body biasing to improve read cell stability SRAM with forward body biasing to improve read cell stability

2006-01-10

2006-01-10

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S226000, C365S189090

Reexamination Certificate

active

06985380

ABSTRACT:
A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

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Wann, C. et al., “CMOS with Active Well Bias for Low-Power and RF/Analog Applications”, IEEE Symposium on VLSI Technology Digest of Technical Papers, 2000, pp. 158-159.
Bhavnagarwala, A. J. et al., “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability”, IEEE Journal of Solid-State Circuits, Apr. 2001, pp. 658-665, vol. 36, No. 4.
Bhavnagarwala, A. J. et al., “Dynamic-Threshold CMOS SRAM Cells for Fast, Portable Applications”, IEEE, 2000, pp. 359-363.

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