SRAM with fast write capability

Details SRAM with fast write capability SRAM with fast write capability

1996-11-22

1999-08-24

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365190, 36518911, 36518905, G11C 700

Patent

active

059432780

ABSTRACT:
In accordance with a preferred embodiment of the invention, the write cycle of an SRAM column is increased. The SRAM column includes at least one SRAM cell connected to the bit line and the bit line complement of the column. Further, a pair of select transistors are located below the bottom SRAM cell, where one select transistor is connected to the bit line and the other is connected to the bit line complement. The select transistors select whether the respective bit line and bit line complement is deselected or selected. The SRAM column further includes a pair of load transistors connected between the bottom SRAM cell and the pair of select transistors, where one of the load transistors is connected to the bit line and the other load transistor is connected to said bit line complement. In operation, since the load transistors are located below the bottom cell, there is no DC current supplied by the load transistors to flow through the entire bit line and bit line complement length. Therefore, the voltage drop potential on the line is reduced which increases the write cycle speed.

REFERENCES:
patent: 5771190 (1998-06-01), Okamura

Affiliated with

Also associated with

Rating

SRAM with fast write capability does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM with fast write capability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM with fast write capability will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-473296