SRAM with current-mode test read data path

Details SRAM with current-mode test read data path SRAM with current-mode test read data path

1996-09-27

2001-09-25

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S207000

Reexamination Certificate

active

06295242

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to static random access memories (SRAMs) and more particularly to SRAMs with a current-mode data path.
BACKGROUND
It has become increasingly difficult to generate and distribute short duration clock pulses on a large scale, for large scale high-speed memories. Such pulses have been required for equalization of the bit lines, etc., but the provision for such pulses prolongs access times and degrades performance of the memory. A current-mode read data path, however, eliminates the need for such clock pulses. Several amplifiers have been described in the literature, but the use of positive feedback to reduce the amplifier input resistance has limited the use of this type of amplifier to single-ended, single stage applications.
A description of a current-mode data path for an SRAM was published in the Apr. 19, 1991 edition of the IEEE Journal of Solid State Circuits. The paper, “Current-Mode Techniques For High-Speed Real Side Circuits”, by E. Seevnick, et al., proposes the use of two complementary current amplifiers as local and global sense amplifiers in an SRAM data path. The detailed design of these amplifiers is, however, different from the amplifier of the present invention. Another paper, “Fast CMOS Current Amplifier And Buffer Stage”, by Cemes and Ki describes a similar single stage current amplifier.
SUMMARY OF THE INVENTION
The present invention employs two cascade complementary differential current amplifiers in a readout circuit for an SRAM. The amplifiers employ special bias circuits and provide improved amplifier operation, allowing them to be connected in series or cascade. A small amplifier differential input resistance reduces the voltage swing of differential lines and thus eliminates the need for equalization clocks.
Whereas in the prior art, the single-ended amplifier has been unsuitable for SRAM data path applications where several stages of differential amplification are required, the amplifiers of the present invention employ a unique bias circuit which improves operation of the amplifiers and extends their use to differential cascaded applications, such as in an SRAM read data path.


REFERENCES:
patent: 4910714 (1990-03-01), Hartgring
patent: 5126974 (1992-06-01), Sasaki
patent: 5229967 (1993-07-01), Nogle
patent: 5291045 (1994-03-01), Atsumi
patent: 5339273 (1994-08-01), Taguchi

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