SRAM operating with a reduced power dissipation

Details SRAM operating with a reduced power dissipation SRAM operating with a reduced power dissipation

2000-11-22

2002-02-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000

Reexamination Certificate

active

06344992

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a SRAM (static random access memory) operating with a reduced power dissipation and, more particularly, to a technique for reduction of power dissipation in a high-speed SRAM having four-transistor
o-load memory cells having a precharge function based on an off-leak current.
(b) Description of the Related Art
A high-speed SRAM which includes an array of four-transistor memory cells each having a precharge function based on an off-leak current is increasingly used for responding to the recent commercial demand for a lower power dissipation and an increased integration of the SRAM. The four-transistor memory cell is also called a no-load memory cell.
FIG. 1
shows a conventional SRAM having four-transistor memory cells, wherein a word line driver
50
and a reference voltage generator
10
Z are disposed for each of the word lines WL
1
which extend in the row direction of a memory cell array. Reference voltage generator
10
Z delivers a precharge voltage VWD directly to the word line driver
50
, which switches the potential of the word line WL
1
activating a row of memory cells
60
between the ground potential and the precharge voltage level VWD. A memory cell
60
is activated for a read/write operation by the ground potential of the corresponding word line WL
1
, wherein the memory cell
60
receives therein data or delivers therefrom data, the data depending on the potentials of the corresponding pair of bit lines BL
1
and BL
2
.
In a precharge operation, both the address signal ADD and the enable signal ENA supplied to the word line driver
50
assume a low level to turn on a pMOSFET Q
41
and turn off an nMOSFET Q
42
in the word line driver
50
, whereby the word line WL
1
assumes the precharge level VWD. The bit lines BL
1
and BL
2
assume a source potential level VCC in this mode. Due to a ratio of two orders in magnitude between the off-leak current of the drive nMOSFETs QN
1
and QN
2
and the off-leak current of the transfer transistors QP
1
and QP
2
, the latter being higher, the storage nodes NC and NB assume a high level and a low level, respectively, for example, based on the original state thereof, whereby the memory cell
60
maintains data “1”. The current I
1
flowing through node N
1
, the current I
2
flowing through node N
2
, both in the reference voltage generator
10
Z, and the current
13
flowing through the storage node NB in the memory cell
60
are equal to one another, due to a current mirror configurations of transistors Q
51
and Q
52
, and of transistors Q
53
and QP
1
, wherein these transistors in each current mirror configuration have an equal transistor size.
FIG. 2
shows the temperature dependency of the off-leak current of nMOSFET and pMOSFET, wherein the off-leak current is plotted on ordinate and the temperature is plotted on abscissa. The difference in the off-leak current between pMOSFET and nMOSFET (or off-leak current difference) increases with a rise of the temperature from 25° C., wherein the off-leak current ratio at 100° C. is almost two orders larger compared to that at a room temperature or 25° C. The off-leak current difference should be larger in view of a stable precharge operation in the SRAM memory cell. However, the off-leak current difference is sometimes too small due to the low ambient temperature or the variations of the transistor characteristics depending on the process conditions during the fabrication thereof. In
FIG. 1
, current
13
, which is equal to current I
1
supplied to the reference voltage generator
10
Z, should be sufficiently larger compared to the off-leak current of drive transistor QN
1
or QN
2
for a stable precharge function.
In the conventional technique, the reference voltage generator
10
Z is disposed for each word line WL
1
, together with the word line driver
50
. This causes a larger chip area for the SRAM. In addition, the word line WL
1
, connected to a row of memory cells
60
, generally has a large parasitic capacitance. Thus, a large voltage fluctuation may arise on the output line of the reference voltage generator
10
Z due to the noise generated on the word line WL
1
having a large parasitic capacitance.
Further, a measure for solving the problem in the small off-leak current difference as described before is not considered in the conventional technique. Thus, for a stable precharge operation, a sufficiently large current should be supplied as current I
1
in the reference voltage generator
10
Z, and the large currents
13
flowing through all the memory cells in the precharge operation increase the power dissipation in the SRAM.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a SRAM including four-transistor
o-load memory cells, which is capable of operating with a lower power dissipation in a stable precharge operation and has a smaller chip area.
The present invention provides a static random access memory (SRAM) including a memory cell array including a plurality of four-transistor memory cells arranged in a matrix, each of said memory cells operating for reading/writing data in a read/write mode or maintaining data in a precharge mode based on an off-leak current, a plurality of word lines each disposed for a corresponding row of the memory cells, a plurality of pairs of bit lines each disposed for a corresponding column of the memory cells, a reference voltage generator for generating a reference voltage, an impedance converter for receiving the reference voltage to deliver a precharge voltage having a lower internal impedance compared to the reference voltage, a word line driver disposed for each of the word lines for switching a corresponding one of the word lines between a read/write potential for the read/write mode and a precharge voltage for the precharge mode.
In accordance with the SRAM of the present invention, the impedance converter connected between the reference voltage generator and the word line drivers affords reduction of the number of reference voltage generators in the conventional SRAM and a stable precharge operation of each memory cell.
The term “precharge” as used in this text means an operation of each memory cell wherein the each memory cell maintains the stored data by using a off-leak current difference between the drive transistors and the transfer transistors thereof while maintaining the gate potential of the transfer transistors at a precharge voltage.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 6205556 (2001-03-01), Watanabe et al.

Affiliated with

Also associated with

Rating

SRAM operating with a reduced power dissipation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM operating with a reduced power dissipation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM operating with a reduced power dissipation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2980218