SRAM method and apparatus

Details SRAM method and apparatus SRAM method and apparatus

1999-09-14

2001-08-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000, C365S185250, C365S189011

Reexamination Certificate

active

06282137

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to static random access memories (SRAMs).
BACKGROUND OF THE INVENTION
SRAMs are read/write memories capable of holding data without the need for frequent refreshing of the contents of the memory cells in the SRAM. In a conventional SRAM, the memory cells are arranged in a series of rows and columns. Referring to
FIG. 1
, which shows the basic structure of the memory array of a conventional SRAM
10
, in each column
12
, all the memory cells
14
are coupled between a BIT line
16
and a {overscore (BIT)} line
18
.
FIG. 1
shows only one column, that column comprising two column segments
12
a
and
12
b
that are alternately selectable via a column select signal
20
that is decoded from the address. However, it should be understood that a typical SRAM comprises many columns. Further, the purpose of segmenting the columns in the manner shown is related to implementation details and particularly to reducing the physical length of the columns relative to the physical width of the memory array. Thus, it should further be apparent to those of skill in the related arts that many SRAMs have simple rows and columns without segmentation.
Each column segment comprises N rows
22
of which only the first row (row
0
) and the last row (row N-
1
) are shown. Each row is coupled to a word select line
24
(sometimes called a row select line) RL(
0
) through RL(N-
1
). The signals on the row select lines
24
are decoded from the address to select a particular row in the memory array. A particular column containing the memory cell being accessed also is decoded from the address to select the single memory cell for reading via a plurality of column select lines, such as column select line
20
.
The BIT lines
16
of each column segment of a single column are coupled together and placed at one input of a sense amplifier
26
. The {overscore (BIT)} lines
18
of each column segment of a column are coupled together and placed at the second input of the sense amplifier
26
. Each column in a multi-column memory has its own sense amplifier. The sense amplifier
26
is controlled by a READ control line. Specifically, the sense amplifier output is latched when the READ line goes unasserted.
In a segmented column memory array as illustrated in
FIG. 1
, transistor switch
28
a
is interposed between each BIT line
16
and the first input of the sense amplifier and another transistor switch
28
b
is interposed between each {overscore (BIT)} line
18
and the corresponding input of the sense amplifier for selecting the one of the two column segments containing the cell which is being accessed by the address. The switches
28
a
and
28
b
are coupled to react complementarily to the same column select signal lines, i.e., CSEL-A
20
and its compliment {overscore (CSEL)}-A. The column select signal essentially is another portion of the decoded address.
Each column segment further comprises a precharge circuit
34
for precharging both the BIT and {overscore (BIT)} lines
16
and
18
of the column segments
12
a
and
12
b
to the same predetermined voltage before a read operation. Particularly, the individual memory cells
14
are coupled between the BIT and {overscore (BIT)} lines of the corresponding column segment such that, during a READ, the cell selected by the decoded address, i.e., the row select line signals
22
and column segment select signals
30
will discharge one and only one of the BIT and {overscore (BIT)} lines depending on whether it is storing a 0 or a 1. The BIT line represents the true value of the stored BIT, while the {overscore (BIT)} line is its complement. All control signals, including the decoded address signals, such as row select and column select, the precharge signal, and the READ signal are shown emanating from a control circuit
37
.
When a cell
14
is read, the sense amplifier
26
detects the differential between the relevant BIT and {overscore (BIT)} line pairs
16
and
18
, latches those values (at the time that the READ line goes unasserted) and amplifies and outputs the corresponding bit value.
The purpose of precharging the BIT and {overscore (BIT)} lines is to reduce the time necessary to read a cell. In particular, it takes substantially more time for a cell to charge a line than it does to discharge it. Accordingly, prior to a READ, both lines are charged by the precharge circuit and the READ operation comprises discharging one of the BIT and {overscore (BIT)} lines.
With the ever present desire to increase memory capacity and speed, many SRAMs currently utilize additional techniques to further decrease READ times. In particular, one class of techniques revolves around the concept of completing the READ before the BIT or {overscore (BIT)} line is completely discharged. In particular, the sense amplifiers typically used in SRAMs require a relatively small voltage differential between their inputs to switch (or, more accurately, to detect the differential between the BIT and {overscore (BIT)} lines coupled at their inputs). For instance, a typical detectable differential voltage threshold across the inputs of a sense amplifier might be about 400 millivolts.
Within this class, there are at least three techniques that are in common use for cutting short the discharge time involved with the READ operation. They are (1) bit line clamping, (2) controlling the on time of the cell access transistors with a delay circuit and (3) controlling the on time of the cell access transistors using a dummy column as a reference. Each of these techniques will be briefly described below. However, those of skill in the art of SRAM design will already be familiar with each of these techniques.
Bit clamping is a technique by which the BIT and {overscore (BIT)} lines are precharged to some voltage less than the VDD (or VSS) voltage. The theory behind bit line clamping is to precharge the BIT and {overscore (BIT)} lines to a voltage only slightly above the necessary threshold voltage for detecting a differential across the sense amplifier. For instance, in a 3 volt circuit (VDD=3 volts and VSS=0 volts,) let us assume that the switch point between a logic high value and a logic low value is 1.5V. Accordingly, with BIT clamping, the BIT and {overscore (BIT)} lines may be precharged to only about 1.8 volts rather than 3 volts. Accordingly, the discharged line (BIT or {overscore (BIT)}) can reach the threshold value much more quickly than if it had been precharged to 3 volts.
FIG. 2
is a circuit diagram of an exemplary precharge circuit employing bit line clamping. As previously noted, the precharge circuit
202
is coupled between the BIT line
204
and the {overscore (BIT)} line
206
of the corresponding column (or column segment). The precharge circuit is of a form conventional in the art and comprises three NMOS transistors
208
,
210
and
212
. Normally, the junction
214
between the transistors
210
and
212
would be coupled directly to the VDD voltage rail. However, with bit line clamping, a diode-coupled PMOS transistor
216
is coupled between VDD and junction
214
. This lowers the voltage to which the precharge circuit will precharge the BIT and {overscore (BIT)} lines
204
and
206
by the threshold voltage of the PMOS transistor
216
. A typical threshold voltage for a PMOS transistor might be 0.6V. Accordingly, in this circuit implementation, the precharge voltage is 2.4 volts rather than 3 volts. If it was desired to drop the precharge voltage from a VDD of 3 volts to, for example, 1.8 volts as discussed previously, there would simply be two BIT line clamping diode coupled transistors coupled in series between VDD and node
214
.
FIG. 3
illustrates an exemplary embodiment of the second aforementioned technique, i.e., controlling the on time of the cell access transistors with a delay. The theory behind this technique is to stop the READ operation and latch the sense amplifier after a sufficient time elapses to assure that the voltage differential across the sense amplifier inputs exceeds the mini

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