SRAM memory device with improved performance

Details SRAM memory device with improved performance SRAM memory device with improved performance

1999-08-23

2000-06-20

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257903, H07L 2711

Patent

active

060780878

ABSTRACT:
A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

REFERENCES:
patent: 5281843 (1994-01-01), Ochii et al.
patent: 5331170 (1994-07-01), Hayashi
patent: 5535155 (1996-07-01), Abe
patent: 5780909 (1998-07-01), Hayashi

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